Abstract: A memory device includes a data array, array control logic, a delay locked loop circuit, timing control logic, and a first storage device. The array control logic is adapted to receive a read command synchronized with an external clock signal and to read at least a first data element from the data array based on the read command. The delay locked loop circuit is adapted to receive the external clock signal and delay the external clock signal by a programmable amount to generate a delay locked loop clock signal. The timing control logic is adapted to generate a first input enable signal based on the external clock signal and a first output enable signal based on the delay locked loop clock signal. The first storage device adapted to receive the first data element. The first storage device has an input terminal enabled in response to the first input enable signal and an output terminal enabled in response to the first output enable signal.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.

Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.

Abstract: A compression test mode, independent of redundancy, for a memory device is disclosed. In one embodiment, a method for testing a memory array of a memory device includes outputting individually the output bits of a predetermined number of memory cells, upon failure of a compression mode. The cells may then be checked for errors and replaced if necessary on an individual basis. In another embodiment, a memory device includes an array of memory cells, and a compression test mode circuit such that only those cells that are defective are replaced with redundant cells. The circuit checks a number of memory cells at one time, however, in a compression test mode.

Abstract: A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.

Abstract: Delay lock loops, signal locking methods, and methods of implementing delay lock loops are described. In one embodiment, a delay lock loop comprises a delay line having first and second inputs and an output. The first input is configured to receive a clock signal. An output model has an input and an output, with the input being operably coupled with the delay line output. The output model is configured to model delays in a system which can be driven by an output clock signal produced by the delay lock loop. A phase detector has a pair of inputs and an output. Phase detector's output is operably coupled with the second input of the delay line. A delay element is interposed between and operably couples both the (a) output of the output model, and (b) the clock signal received by the delay line, with respective inputs of the phase detector. The delay element is configured to present an additional delay to the phase detector which is in addition to the modeled delay provided by the output model.

Abstract: A method and circuit for testing cells in a memory device is disclosed. Data is written to the cells and then the cells are read in groups. For example, groups of four cells are read together. Output bits of the four cells are compressed in a compression circuit to generate compressed data, and the compressed data is checked to determine if one or more of the four cells was defective and produced an incorrect output bit. If one of the cells was defective, each cell is read in a sequence and its output bit is tested to determine which of the four cells is defective. The defective cell is replaced with a redundant cell.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.

Abstract: A programmable bandwidth I/O port using a DRAM connected to a plurality of serial access memories. Data is synchronously transferred between the DRAM and the serial access memories and is asynchronously transferred between the serial access memories and a plurality of single or multiple bit I/O ports. The bus widths of the I/O ports may be easily programmed to provide a wide variety of I/O port configurations.

Abstract: A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.

Abstract: A multiport switch buffers and transfers cells of digital data. It provides the ability to control the synchronization of the ports in a distributed manner. Each port is associated with a counter that starts counting when transmission by either the port it is associated with is transferring a cell, or when another port is transferring a cell on a channel that conflicts with the channel attached to the port. The counter counts the appropriate number of digits corresponding to the length of the cell whereupon the port is provided with a signal indicating that the transmission has ended. In association with other control signals, the port may then begin transmitting a new cell. When multiple switches are attached to the same channel, the counter serves as a self-queuing mechanism that relieves a central controller from having to keep track of the transmission of bits by each port, and from having to select the next port for transmission.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.).