Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: A switcher system or circuit and corresponding methods provide dynamic voltage scaling. One embodiment of an apparatus includes: a switcher controller configured to monitor a signal from a processor for a first state, determine a time that the signal is in the first state, and provide an adjustment signal based on the time, and a power supply coupled to the adjustment signal and configured to provide a variable supply voltage to the processor core, the variable supply voltage controlled by the adjustment signal after the determining a time.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol.

Abstract: A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: A switcher system or circuit and corresponding methods provide dynamic voltage scaling. One embodiment of an apparatus includes: a switcher controller configured to monitor a signal from a processor for a first state, determine a time that the signal is in the first state, and provide an adjustment signal based on the time, and a power supply coupled to the adjustment signal and configured to provide a variable supply voltage to the processor core, the variable supply voltage controlled by the adjustment signal after the determining a time.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol.

Abstract: A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.

Abstract: A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

Abstract: An integrated circuit (103) having a plurality of integrated circuit portions (111, 113, and 115) where each of the plurality of integrated circuit portions receives a corresponding voltage of a plurality of voltages. Selection circuitry (127 and 123) selects a selected voltage of the plurality of voltages and provides an indication of the selected voltage to adjust the supply voltage to the integrated circuit. in one embodiment, the indication may correspond to an analog signal proportional to the selected voltage such as e.g. at the selected voltage or at a voltage less than or greater than the selected voltage. A power supply system (105), coupled to the integrated circuit, may be used to receive the indication of the selected voltage and adjust the supply voltage based on the indication.

Abstract: A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.

Abstract: Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.

Abstract: A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.