Abstract: Semiconductor devices with high current capability for ESD or surge protection are described. The semiconductor device includes multiple n-type semiconductor regions in a p-type semiconductor layer. Each of the n-type semiconductor regions may have a footprint with a circular, oval, or obround shape. Moreover, a boundary of the footprint may be spaced apart from an isolation structure that surrounds the p-type semiconductor layer. The n-type semiconductor regions may be coupled to a terminal through individual groups of contacts that are connected to the n-type semiconductor regions, respectively. Additionally, or alternatively, the p-type semiconductor layer surrounded by the isolation structure may not include any re-entrant corner.

Abstract: Electrostatic discharge (ESD) protection devices with high current capability are described. The ESD protection device may include a pair of bidirectional diodes (first and second bidirectional diodes) connected in series. Each of the bidirectional diodes includes a low capacitance (LC) diode and a bypass diode connected in parallel. During ESD events, current flows through the LC diode of the first bidirectional diode and the bypass diode of the second bidirectional diode. Particular arrangements of the LC diodes and the bypass diodes are devised to facilitate uniform distribution of the current throughout an area occupied by the ESD protection device.

Abstract: A semiconductor switching circuit associated with a power semiconductor circuit is described. The semiconductor switching circuit includes a snubber circuit comprising a snubber switch element that comprises a first terminal configured to couple to a supply node associated with the power semiconductor circuit and a second terminal configured to couple to a switch node associated with the power semiconductor circuit. In some aspects, the snubber switch element is configured to bypass a ringing voltage at the switch node associated with the power semiconductor circuit to the supply node associated with the power semiconductor circuit. In some aspects, the ringing voltage at the switch node comprises a voltage that is greater than a supply voltage associated with the supply node.

Abstract: A semiconductor switching circuit associated with a power semiconductor circuit is described. The semiconductor switching circuit includes a snubber circuit comprising a snubber switch element that comprises a first terminal configured to couple to a supply node associated with the power semiconductor circuit and a second terminal configured to couple to a switch node associated with the power semiconductor circuit. In some aspects, the snubber switch element is configured to bypass a ringing voltage at the switch node associated with the power semiconductor circuit to the supply node associated with the power semiconductor circuit. In some aspects, the ringing voltage at the switch node comprises a voltage that is greater than a supply voltage associated with the supply node.

Abstract: A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.

Abstract: A field effect transistor is disclosed. In one embodiment, the field effect transistor includes a trench extending into a drift region of the field effect transistor. A shield electrode in a lower portion of the trench is insulated from the drift region by a shield dielectric. A gate electrode in the trench over the shield electrode is insulated from the shield electrode by an inter-electrode dielectric. A source region is formed adjacent the trench. A resistive element is coupled to the shield electrode and to a source region in the field effective transistor.

Abstract: A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

Abstract: A charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current when biased in a conducting state. A non-active perimeter region surrounds the active area, wherein no current flows through the non-active perimeter when the plurality of cells is biased in a conducting state. Alternately arranged strips of p pillars and strips of n pillars extend through both the active area and the non-active perimeter region along a length of a die housing the semiconductor power device.

Abstract: A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.

Abstract: A semiconductor power transistor includes a drift region of a first conductivity type and a well region of a second conductivity type in the drift region such that the well region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type is in the well region, and a second highly doped silicon region is in the drift region. The second highly doped silicon region is laterally spaced from the well region such that upon biasing the transistor in a conducting state, a current flows laterally between first and second highly doped silicon regions through the drift region. Each of a plurality of trenches extending into the drift region perpendicular to the current flow includes a dielectric layer lining at least a portion of the trench sidewalls and at least one conductive electrode.

Abstract: PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.

Abstract: In accordance with an embodiment of the invention, a semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. A first silicon region of a first conductivity type extends to a first depth within a second silicon region of a second conductivity type, the first and second silicon regions forming a PN junction therebetween. At least one termination trench is formed in the termination. The termination trench extends into the second silicon region, and is laterally spaced from the first silicon region. An insulating layer lines the sidewalls and bottom of the termination trench. A conductive electrode at least partially fills the termination trench.

Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

Abstract: A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.

Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Abstract: A semiconductor structure is formed as follows. A semiconductor region is formed to have a P-type region and a N-type region forming a PN junction therebetween. A first trench is formed extending in the semiconductor region adjacent at least one of the P-type and N-type regions is formed. At least one diode is formed in the trench.

Abstract: An integrated buck converter is formed on a substrate of a first polarity type and having a first and second substrate surface. An epitaxial layer is formed over the first substrate surface and has a first epitaxial layer surface. A drift region lightly-doped with dopants of a second polarity type opposite the first polarity type is disposed within a first portion of the epitaxial layer. A high-side transistor is formed in the drift region. A low-side transistor is formed in a second portion of the epitaxial layer outside the drift region. A combined high-side source and low-side drain contact is disposed over the second substrate surface. Means for connecting the high-side source to the combined high-side source and low side drain contact are provided.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.