Abstract: a Schottky diode having a semiconductor region is formed as follows. A plurality of charge control electrodes are formed in the semiconductor region so as to influence an electric field in the semiconductor region, wherein at least two of the charge control electrodes are adapted to be biased differently from one another. The semiconductor region is overlaid with a metal layer to thereby form a Schottky barrier therebetween.

Abstract: In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

Abstract: An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity type. The transistor further includes a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the conduction region and the channel regions. A number of charge balancing structures are integrated with the semiconductor region so as to extend parallel to the current flow. In a blocking state, the charge balancing structures influence an electric field in the conduction region so as to increase the blocking capability of the accumulation-mode field effect transistor.

Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: A method for reducing miller capacitance and switching losses in an integrated circuit includes providing a switching gate electrode having respective portions that are coplanar with the source and well regions of the integrated circuit. The switching gate electrode is configured for switching the integrated circuit on and off in response to a relatively small change in applied voltage. A shielding gate electrode is formed with respective portions coplanar with the switching electrode and the well region. The shielding electrode is configured for charging the gate-to-drain overlap region of the integrated circuit.