Abstract: Aspects of the present disclosure are directed to techniques and apparatuses for implementing a power-on (PON) sequence in a computer system. A power management integrated circuit (PMIC) receives a boot circuit indicator (BCI) signal from a computer system. The BCI signal identifies a circuit of the computer system to be enabled in a power-on (PON) sequence. The PMIC provides power to the boot core or cluster of the SoC based on the BCI signal.

Abstract: Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.

Abstract: Various embodiments include systems and methods for balancing battery cycles of paired earbuds. A processor in an earbud charging case may receive battery level information from a first earbud operating in a deep sleep mode, determine a battery differential index (BDI) value, and send an instruction message to the first earbud indicating the first earbud should switch roles with a second earbud. An earbud may start a timer upon beginning to operate in a dormant mode, transition from operating in the dormant mode to operating in a non-dormant mode in response to expiration of the timer, send a message to a paired earbud indicating that the earbud has transitioned, and receive a message from the paired earbud indicating that the earbud should switch from operating in the dormant mode to operating in the deep sleep mode and periodically broadcasting an advertisement.

Abstract: A subordinate device participates in address assignment through iterative communication with a host device. The subordinate device receives a first broadcast command over a multidrop serial bus, decouples a daisy chain input of the subordinate device from a daisy chain output of the subordinate device, receives a second broadcast command over the multidrop serial bus, responds to the second broadcast command when a signal received through the daisy chain input is in an active state, ignores the second broadcast command when the signal received through the daisy chain input is in an inactive state, and ignores subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the subordinate device using an address provided in the second broadcast command, and coupling the daisy chain input of the subordinate device to the daisy chain output of the subordinate device.

Abstract: Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.

Abstract: A hybrid circuit board device includes a hybrid circuit board with a second, child circuit board disposed into a recessed circuit board portion of a first, parent circuit board to combine functionality of the child circuit board and the parent circuit board without exceeding a maximum circuit board height. The parent circuit board includes a first circuit board portion having a first thickness in a thickness direction. First interconnects on the first circuit board portion can couple to a first IC component. The child circuit board includes second interconnects to couple a second IC component. The child circuit board is in the recessed circuit board portion and is coupled to the parent circuit board by at least one board interconnect. The recessed circuit board portion of the parent circuit board has a second thickness that is thinner, in the thickness direction, than the first thickness.

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

Abstract: Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device (“PCD”) are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may “sleep” while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.

Abstract: Features in a portable computing device (“PCD”) may be selected for disabling by reading configuration information indicating one or more PCD features and corresponding state information. The state information may be written to one or more registers to provide a register with a state indicating that a PCD hardware feature corresponding to the register is either enabled or disabled. Each register may then be locked against a change of state. Each register may have an output coupled to an enabling signal input of a corresponding PCD hardware feature.

Abstract: An intelligent sorting apparatus includes sensors, bins, and a controller that is configured to use data from the sensors to intelligently sort items into one of the plurality of bins. The controller may use the sensors to determine whether an item includes one of ceramic, metal, or wet or dry waste, as the item traverses down a first, second, and/or third incline, respectively. The controller may route the item towards one of a ceramic bin when the item includes ceramic, metal bin when the item includes metal, wet bin when the item includes wet waste, or dry bin when the item includes dry waste.

Abstract: An intelligent sorting apparatus includes sensors, bins, and a controller that is configured to use data from the sensors to intelligently sort items into one of the plurality of bins. The controller may use the sensors to determine whether an item includes one of ceramic, metal, or wet or dry waste, as the item traverses down a first, second, and/or third incline, respectively. The controller may route the item towards one of a ceramic bin when the item includes ceramic, metal bin when the item includes metal, wet bin when the item includes wet waste, or dry bin when the item includes dry waste.

Abstract: Systems, methods, and apparatus related to the operation of a multilane serial bus communicate the configuration of lanes used to handle a transaction over the serial bus through signaling transmitted at the commencement of the transaction. The method includes asserting a multilane bus request by initiating a pulse on a secondary data lane of the serial bus while the clock lane is idle, participating in a first bus arbitration procedure executed using the secondary data lane after the pulse is terminated, providing initial signaling on the secondary data lane after winning the first bus arbitration procedure to indicate a set of data lanes to be used during a transaction, and executing a first transaction using the set of data lanes. The set of data lanes may include the primary data lane and the secondary data lane. The initial signaling may include a sequence start condition.

Abstract: Systems, methods, and computer programs are provided for controlling power in a computing device. One embodiment is a system comprising a plurality of power rails coupled to one or more computing device components. Each power rail has a primary power supply for producing current at a corresponding requested voltage. The system further comprises a shared secondary power supply selectively coupled to the plurality of power rails for providing a current increase. A controller selects one of the plurality of power rails to receive the current increase. The controller generates a control signal to electrically couple the shared secondary power supply to the selected power rail to receive the current increase.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.