Abstract: Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.

Abstract: An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Abstract: A storage device is pre-loaded with an access block including a list of device addresses with which the device is either permitted or not permitted to communicate over a shared bus prior to a bootloader being initiated on the device. A communication circuit is coupled to the storage device, and the circuit is adapted to: (a) obtain a first command to be transmitted over the shared bus to a first device address; (b) determine whether the first device address is in the list of device addresses in the access block; and (c) allow or prevent transmission of the first command over the shared bus based on whether the firt device address is in the list of device addresses. The list of device addresses is bypassed or ignored after the bootloader procedure is completed.

Abstract: Systems and methods are disclosed method for operating a serial interconnect of a computer system in a time deterministic manner. An exemplary method comprises that a command to be sent over the serial interconnect in a transaction is to be executed at a specific time. A delay period for the command to be sent from a master of the computer system to a slave of the computer system via the serial bus is determined, where the delay period determined based on a length of an arbitration phase of the transaction. The command is then sent to the slave of the computer system via the serial bus after the delay period.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

Abstract: Systems, methods, and apparatus for communicating a control signal between device components are provided. Within an apparatus, an integrated circuit (IC) sends a control signal to a system on chip (SoC). The control signal requests enablement or disablement of one or more resources corresponding to the IC. Thereafter, a converting circuit within the SoC converts the control signal from the IC into a command to be transmitted to one or more devices. The converting circuit then transmits the command to the one or more devices via a bus coupling the SoC to the one or more devices. The one or more devices includes one or more power management integrated circuits (PMICs) configured to control the one or more resources.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: A mobile device having parallel use of non-volatile memory and main memory is presented. The mobile device includes a volatile memory, a non-volatile memory, a memory controller functionally coupled to the non-volatile memory and the volatile memory, and a processor coupled to the memory controller. The processor addresses both the non-volatile memory and the volatile memory utilizing a continuous memory map. Alternatively, a mobile device may include a volatile memory, a non-volatile memory, a memory controller coupled to the volatile memory, a processor coupled to the memory controller. The processor may address the volatile memory during normal operation. The mobile device may further include a shadow copy controller coupled to the non-volatile memory and the memory controller, where the shadow copy controller copies information stored in a designated portion of the volatile memory into the non-volatile memory.

Abstract: An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Abstract: The present disclosure describes aspects of managing communication control for wireless power transfer. In some aspects, a method for managing wireless charging communications is provided. The method includes wirelessly receiving power from a wireless power transmitter and providing the wirelessly received power to a power management circuit. The method further includes providing power and a power source indication signal to a transceiver circuit. The power source indication signal is indicating the power is the wirelessly received power.

Abstract: Systems and methods are disclosed resetting a slave identification (SID) of an integrated circuit (IC). An exemplary method comprises determining that a plurality of ICs in communication with a shared bus have the same SID, the shared bus operating in a master/slave configuration. A common memory address of the ICs is identified, where data stored in the common memory address is different for a first IC and a second IC. Each of the ICs receives over the shared bus a new SID value and match data. The ICs compare the match data with the data stored in the common memory address. If the match data is the same as the data in the common memory address, the SID is changed the received new SID value.

Abstract: Systems and methods are disclosed resetting a slave identification (SID) of an integrated circuit (IC). An exemplary method comprises determining that a plurality of ICs in communication with a shared bus have the same SID, the shared bus operating in a master/slave configuration. A common memory address of the ICs is identified, where data stored in the common memory address is different for a first IC and a second IC. Each of the ICs receives over the shared bus a new SID value and match data. The ICs compare the match data with the data stored in the common memory address. If the match data is the same as the data in the common memory address, the SID is changed the received new SID value.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

Abstract: System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

Abstract: A system and method providing for delayed initialization of a device in a wireless charging environment. In certain aspects, a device is configured to detect power wirelessly received from a power transmitter. The device may further wirelessly transmit a message to the power transmitter in response to the received power, further determining that a power level of the received power has been adjusted in response to the message. In response to the determining the power level has been adjusted, a controller that is powered by the adjusted power level may be initialized.

Abstract: System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.