Patents by Inventor Christopher L. Rumer
Christopher L. Rumer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11222877Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.Type: GrantFiled: September 29, 2017Date of Patent: January 11, 2022Assignee: Intel CorporationInventors: Omkar Karhade, Robert L. Sankman, Nitin A. Deshpande, Mitul Modi, Thomas J. De Bonis, Robert M. Nickerson, Zhimin Wan, Haifa Hariri, Sri Chaitra J. Chavali, Nazmiye Acikgoz Akbay, Fadi Y. Hafez, Christopher L. Rumer
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Patent number: 11056466Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.Type: GrantFiled: August 27, 2019Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
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Publication number: 20190385983Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Applicant: Intel CorporationInventors: OMKAR KARHADE, CHRISTOPHER L. RUMER, NITIN DESHPANDE, ROBERT M. NICKERSON
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Patent number: 10438930Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.Type: GrantFiled: June 30, 2017Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Omkar Karhade, Christopher L. Rumer, Nitin Deshpande, Robert M. Nickerson
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Publication number: 20190103385Abstract: The present disclosure is directed to systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A thermally conductive member that includes at least one thermally conductive member may be disposed between the first semiconductor package and the second semiconductor package. The thermally conductive member may include: a single thermally conductive element; multiple thermally conductive elements; or a core that includes at least one thermally conductive element. The thermally conductive elements are thermally conductively coupled to an upper surface of the first semiconductor package and to the lower surface of the second semiconductor package to facilitate the transfer of heat from the first semiconductor package to the second semiconductor package.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: OMKAR KARHADE, ROBERT L. SANKMAN, NITIN A. DESHPANDE, MITUL MODI, THOMAS J. DE BONIS, ROBERT M. NICKERSON, ZHIMIN WAN, HAIFA HARIRI, SRI CHAITRA J. CHAVALI, NAZMIYE ACIKGOZ AKBAY, FADI Y. HAFEZ, CHRISTOPHER L. RUMER
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Publication number: 20190006319Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: OMKAR KARHADE, CHRISTOPHER L. RUMER, NITIN DESHPANDE, ROBERT M. NICKERSON
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Publication number: 20170154828Abstract: A method and machine-readable medium including non-transitory program instructions that when executed by a processor cause the processor to perform a method including measuring at least one parameter of a substrate or a die; and establishing or modifying a thermal compression bonding recipe based on the at least one parameter, wherein the thermal compression bonding recipe is operable for thermal compression bonding of the die and the substrate. A thermal compression bonding tool including a pedestal operable to hold a substrate during a thermal compression bonding process and a bond head operable to engage a die, the tool including a controller machine readable instructions to process a substrate and a die combination, the instructions including an algorithm to implement or modify a thermal compression bonding process based on a parameter of a substrate or die.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Inventors: Timothy A. GOSSELIN, Patrick NARDI, Kartik SRINIVASAN, Amram EITAN, Ji Yong PARK, Christopher L. RUMER, George S. KOSTIEW
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Patent number: 8193072Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: November 2, 2010Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7996989Abstract: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.Type: GrantFiled: April 3, 2008Date of Patent: August 16, 2011Assignee: Intel CorporationInventors: Ashay A. Dani, Sabina J. Houle, Christopher L. Rumer, Thomas J Fitzgerald
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Publication number: 20110059596Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: ApplicationFiled: November 2, 2010Publication date: March 10, 2011Inventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7897486Abstract: Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.Type: GrantFiled: May 9, 2007Date of Patent: March 1, 2011Assignee: Intel CorporationInventors: Eric J. Li, Daoqiang Lu, Christopher L. Rumer, Paul A. Koning, Darcy E. Fleming, Gudbjorg H. Oskarsdottir, Tiffany Byrne
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Patent number: 7846778Abstract: An integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and a method of making an electronic assembly.Type: GrantFiled: October 2, 2002Date of Patent: December 7, 2010Assignee: Intel CorporationInventors: Christopher L. Rumer, Sabina J. Houle, Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Patent number: 7619318Abstract: In some embodiments, a method includes providing a composition which includes a base at least partially filled with filler particles and applying the composition as an underfill composition. At least some of the filler particles are electrically conductive.Type: GrantFiled: September 29, 2005Date of Patent: November 17, 2009Assignee: Intel CorporationInventors: Christopher L. Rumer, Tian-An Chen, Vijay Wakharkar, Paul A. Koning
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Patent number: 7611966Abstract: A method is described for laser scribing or dicing portions of a workpiece using multi-source laser systems. In one embodiment, a first laser melts portions of the workpiece prior to a second laser ablating the portions of the workpiece.Type: GrantFiled: May 5, 2005Date of Patent: November 3, 2009Assignee: Intel CorporationInventors: Eric J. Li, Sergei L. Voronov, Christopher L. Rumer
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Patent number: 7527090Abstract: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.Type: GrantFiled: June 30, 2003Date of Patent: May 5, 2009Assignee: Intel CorporationInventors: Ashay A. Dani, Sabina J. Houle, Christopher L. Rumer, Thomas J Fitzgerald
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Patent number: 7473995Abstract: An integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and a method of making an electronic assembly.Type: GrantFiled: March 25, 2002Date of Patent: January 6, 2009Assignee: Intel CorporationInventors: Christopher L. Rumer, Sabina J. Houle, Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Publication number: 20080185713Abstract: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.Type: ApplicationFiled: April 3, 2008Publication date: August 7, 2008Inventors: Ashay A. Dani, Sabina J. Houle, Christopher L. Rumer, Thomas J Fitzgerald
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Patent number: 7358606Abstract: A device and method identify and compensate for tensile stress due to heat-caused expansion and contraction between an integrated heat spreader and thermal interface material. This device and method change the shape of the integrated heat spreader based upon the identification of the location of the highest tensile and/or shear stress so that additional thermal interface material is deposited between the integrated heat spreader and a die. Utilizing this method and device, heat is efficiently transferred from the die to the integrated heat spreader.Type: GrantFiled: May 28, 2004Date of Patent: April 15, 2008Assignee: Intel CorporationInventors: Christopher L. Rumer, Sabina J. Houle
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Patent number: 7311967Abstract: A thermal interface material is described for thermal coupling of an electronic component to a thermally conductive member. The thermal interface material includes a viscoelastic polymer matrix material, fusible solder particles in the matrix material, and filler particles in the matrix material. The solder particles have a melting temperature below a selected temperature (e.g. 157° C. for indium) and the filler particles have a melting temperature substantially above the selected temperature (e.g. 961° C. for silver). The filler particles keep the thermal interface material intact under adverse thermal and stress conditions.Type: GrantFiled: October 18, 2001Date of Patent: December 25, 2007Assignee: Intel CorporationInventors: Ashay A. Dani, Paul A. Koning, Saikumar Jayaraman, Christopher L. Rumer
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Patent number: 7303977Abstract: A laser micromachining method is disclosed wherein a workpiece is milled using an incident beam from a laser beam focused above the surface of the workpiece. The incident beam is guided by a plasma channel generated by the incident beam. The plasma channel, which has a relatively constant diameter over an extended distance, is generated by continual Kerr effect self-focusing balanced by ionization of air beam defocusing.Type: GrantFiled: November 10, 2004Date of Patent: December 4, 2007Assignee: Intel CorporationInventors: Sergei L. Voronov, Christopher L. Rumer