Patents by Inventor Christopher M. Durham
Christopher M. Durham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090114913Abstract: A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Applicant: International Business Machines CorporationInventors: Kerry Bernstein, Jerome L. Cann, Christopher M. Durham, Paul D. Kartschoke, Peter J. Klim, Donald L. Wheater
-
Publication number: 20090106708Abstract: A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.Type: ApplicationFiled: May 29, 2008Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rafik F. Dagher, Christopher M. Durham, Peter J. Klim
-
Publication number: 20090102509Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.Type: ApplicationFiled: October 23, 2007Publication date: April 23, 2009Inventors: Rafik Dagher, Christopher M. Durham, Peter J. Klim
-
Publication number: 20090096486Abstract: A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.Type: ApplicationFiled: February 11, 2008Publication date: April 16, 2009Inventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Robert N. Krentler, James D. Warnock
-
Patent number: 7511529Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.Type: GrantFiled: October 23, 2007Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Rafik Dagher, Christopher M. Durham, Peter J. Klim
-
Publication number: 20090072863Abstract: A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.Type: ApplicationFiled: October 23, 2008Publication date: March 19, 2009Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Robert N. Krentler, James D. Warnock
-
Patent number: 7466164Abstract: A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: GrantFiled: June 7, 2007Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, James D. Warnock
-
Patent number: 7466165Abstract: A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.Type: GrantFiled: September 13, 2007Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Robert N. Krentler, James D. Warnock
-
Publication number: 20080303553Abstract: A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Inventors: OWEN CHIANG, Christopher M. Durham, Peter J. Klim, James D. Warnock
-
Publication number: 20080303554Abstract: A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: ApplicationFiled: June 3, 2008Publication date: December 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Owen CHIANG, Christopher M. Durham, Peter J. Klim, James D. Warnock
-
Publication number: 20080229260Abstract: A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.Type: ApplicationFiled: May 30, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORP.Inventors: CHRISTOPHER M. DURHAM, Peter J. Klim, Robert N.L. Krentler
-
Publication number: 20080215941Abstract: A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a scan clock generation circuit for generating first and second scan clock signals; a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, the scannable pulse flip-flop circuit including a scan input and a scan output connected with the internal storage node, and receptive to the pulse clock signal and the scan clock signals. The scannable pulse flip-flop circuit is configured to be operable in a function mode of operation and a scan mode of operation.Type: ApplicationFiled: May 19, 2008Publication date: September 4, 2008Applicant: International Business Machines CorporationInventors: Christopher M. Durham, Jenny Fan, Peter J. Klim, Robert N. Krentler
-
Publication number: 20080082882Abstract: A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock and first and second scan clock signals. The circuit further includes a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, and a scan input and a scan output that are also connected with the internal storage node. In a function mode of operation, the first and second scan clock signals are held at a logic level to allow data to pass from the data input to the internal storage node at the first clock pulse and from the internal storage node to the data output at the second clock pulse signal.Type: ApplicationFiled: September 13, 2006Publication date: April 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher M. Durham, Jenny Fan, Peter J. Klim, Robert N. Krentler
-
Publication number: 20080016475Abstract: A method of tuning an integrated circuit design includes holding a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizing transistors forming a register within the integrated circuit design and thereafter optimizing transistors forming one or more clock buffers coupled to the reference clock signal.Type: ApplicationFiled: July 13, 2006Publication date: January 17, 2008Inventors: Christopher M. Durham, Peter J. Klim, Robert N. L. Krentler
-
Patent number: 6832277Abstract: A method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes: broadcasting a first portion of data that includes N/2 bits of data onto the first plurality of electrical conductors. Then, after a time period has elapsed that is greater than 0 seconds and less than the time period required to transfer 2 bits of data sequentially on one of the first plurality of electrical conductors, broadcasting a second portion of data that includes N/2 bits of data onto the second plurality of electrical conductors.Type: GrantFiled: August 2, 2001Date of Patent: December 14, 2004Assignee: Sun Microsystems, Inc.Inventors: Christopher M. Durham, Parsotam T. Patel
-
Publication number: 20040178825Abstract: According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.Type: ApplicationFiled: March 13, 2003Publication date: September 16, 2004Applicant: International Business Machines CorporationInventors: Matthew J. Amatangelo, Taqi Nasser Buti, Christopher M. Durham, Peter Juergen Klim
-
Patent number: 6791363Abstract: According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.Type: GrantFiled: March 13, 2003Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Matthew J. Amatangelo, Taqi Nasser Buti, Christopher M. Durham, Peter Juergen Klim
-
Publication number: 20040150449Abstract: A high-speed, noise-safe, non-inverting flip-flop (“flop”) is provided. In the flop, a buffer is used to isolate a data input terminal from the remainder of the flop circuitry to prevent erroneous operation of the flop circuitry. Also, a slave node is connected to a master node to avoid the need for an additional buffer on a data signal critical path, thus preserving the high-speed of the flop circuitry. Overlapped clock signals are used to control data signal transmission to the master node and the slave node. The overlapped clock signals allow the buffer used to isolate the data input terminal to also be used to drive the data signal through the master node to the slave node.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Applicant: Sun Microsystems, Inc.Inventors: Christopher M. Durham, Hang B. Lauv, Robert T. Golla
-
Patent number: 6650592Abstract: A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.Type: GrantFiled: November 29, 2001Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Matthew J. Amatangelo, Christopher M. Durham, Peter Juergen Klim
-
Publication number: 20030099129Abstract: A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.Type: ApplicationFiled: November 29, 2001Publication date: May 29, 2003Applicant: International Business Machines CorporationInventors: Matthew J. Amatangelo, Christopher M. Durham, Peter Juergen Klim