Abstract: A method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes: broadcasting a first portion of data that includes N/2 bits of data onto the first plurality of electrical conductors. Then, after a time period has elapsed that is greater than 0 seconds and less than the time period required to transfer 2 bits of data sequentially on one of the first plurality of electrical conductors, broadcasting a second portion of data that includes N/2 bits of data onto the second plurality of electrical conductors.

Abstract: A master-slave flip-flop circuit (200, 200′) includes a master latch circuit (202) and slave latch circuit (203). A hold control component (220) included in the master latch circuit (202) is interposed between a master latch node (ML) and a slave input node (SI). The hold control component blocks the transfer of data from the master latch node (ML) to the slave input node (SI) in response to a hold input. In the preferred form of the invention of the hold control component (220) comprises a tri-state inverter having an input connected to the master latch node (ML) and an output connected to the slave input node (SI). The hold input, comprising a high level hold signal and its complementary or inverted signal, disables the tri-state inverter and thus prevent data from being transferred from the master latch node (ML) to the slave input node (SI).

Abstract: An extended segmented precharge architecture for static random access memories includes a logic circuitry on an SRAM chip to keep track as to whether a given bit line has been read out. As long as a given bit line has not been read out, precharge of the equalization lines is eliminated thereby increasing access cycle time and reducing power dissipation. The architecture can be applied to any size SRAM of any organization.

Abstract: A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them.

Abstract: A logic filtered address transition detection circuit that receives a chip select signal and an ATD pulse, and which produces an internal clock pulse using:an AND gate, a filtered input terminal, a delay unit and a comparator unit. The AND gate outputs an AND logic signal after processing the chip select signal and ATD pulse, the filtered input terminal and delay unit both receive the AND logic signal from the AND gate; and send their signals to the comparator unit. The comparator unit performs a logic function on the AND logic signal and a delayed AND logic signal to produce the internal clock signal.

Abstract: A forward single-rail self-resetting reset circuit is utilized to reset a logic circuit to a selected state subsequent to each iteration of a logical operation on inputted data into the logic circuit. The reset circuit receives at least one of the data inputs and its complement signal so that the reset signal produced by the reset circuit is activated regardless of the voltage level of the data input signals.

Abstract: A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to select mode, there appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such a false transition as an actual transition, local clock pulse generators are used which only detect high to low transitions in the chip select mode.

Abstract: A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.

Abstract: A fused, redundancy selection circuit is disclosed which is disabled by the absence of a chip select signal. The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristic. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off.