Abstract: A mailing machine for the creation of mailpieces includes a print station and a transport system for passing a length of the label material through the print station to receive information on a face surface of the label material. A processor is adapted to store rating information based upon the weight and dimensions of the mailpiece and is operatively coupled to, and controls, the print station and transport system. In a first operating mode, the processor prints rating information on a length of label material, and in a second operating mode, the processor prints postage indicia on the face surface of the label material based upon the rating information for subsequent application to a mailpiece. In the second operating mode, the postage indicia may optionally be printed on the label material or directly on the face surface of the mailpiece envelope.

Abstract: A mailing machine for the creation of mailpieces includes a print station and a transport system for passing a length of the label material through the print station to receive information on a face surface of the label material. A processor is adapted to store rating information based upon the weight and dimensions of the mailpiece and is operatively coupled to, and controls, the print station and transport system. In a first operating mode, the processor prints rating information on a length of label material, and in a second operating mode, the processor prints postage indicia on the face surface of the label material based upon the rating information for subsequent application to a mailpiece. In the second operating mode, the postage indicia may optionally be printed on the label material or directly on the face surface of the mailpiece envelope.

Abstract: A mail processing system and method that will that reduce clogging of the print head nozzles due to the use of different inks is provided. When an ink tank is being replaced in a mailing system, the system controller determines if the ink in the new ink tank is a known ink type that is deemed to be compatible with the ink from the ink tank being replaced. If the new ink is deemed to be not compatible with the ink from the tank being replaced, a maintenance operation is performed to remove the ink from the ink tank being replaced that may remain in the supply path and print head from the system. By removing the ink remaining from the ink tank being replaced out of the system, there is minimal ink left in the supply path or print head to mix with the new ink.

Abstract: A method includes receiving, in a postage meter, input from a user to select a rate option in the postage meter for mail that is to be pre-sorted at a remote location. If the selected pre-sort rate option has been programmed into the postage meter, the postage meter is set to print postage indicia in accordance with the selected pre-sort rate option. If the selected pre-sort rate option has not been programmed into the postage meter, the postage meter displays, to the user, information to indicate to the user how to arrange for the selected pre-sort rate option to be programmed into the postage meter.

Abstract: A circuit generally comprising a plurality of master modules and a supervisor module is disclosed. The supervisor module may be configured to (i) detect a target address and a particular master module of the master modules initiating a transaction on a bus, (ii) identify a predetermined authorization in response to the particular master module, the target address and a current security mode of at least three security modes and (iii) subvert the transaction in response to the predetermined authorization restricting the transaction.

Abstract: A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a second memory. The processor may have a pipeline and may be configured to (i) bootstrap to the first memory while the register stores a highest security value of the security values and (ii) execute the jump instruction following the write instruction. The logic block may be configured to (i) detect the write instruction in an execution stage of the pipeline and (ii) store the non-highest security value in the register in response to detecting the write instruction in a write back stage of the pipeline.

Abstract: A circuit generally comprising a logic module and a security module is disclosed. The logic module may be configured to set a plurality of values to a plurality of predetermined values respectively while in a scan mode. The security module may be configured to (i) disable a scan capability of the values while in a non-lowest security mode of at least three security modes and (ii) enabling the scan capability while in a lowest security mode of the security modes.

Abstract: A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.

Abstract: An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

Abstract: A circuit generally comprising a first memory, a second memory and a processor is disclosed. The first memory may store an instruction to read an updated security value of at least three security values. The second memory may store (i) the updated security value and (ii) information related to security of the circuit. The processor may be configured to (i) execute the instruction while a register stores a highest security value of the security values, (ii) copy the information from the second memory to a third memory in response to the update security value being greater than a current security value of the security values stored in the third memory and (iii) ignore the information in the second memory in response to the updated security value being no greater than the current security value.

Abstract: Ownership of a peripheral bus between a peripheral device and a plurality of master devices is assigned to one of the master devices. Each master device has an associated controller for controlling the peripheral device via the peripheral bus. Communication occurs without impediment between the master device and its controller that have ownership of the bus, thereby conducting transactions via the peripheral bus and peripheral device. Communication with the master device and controller not having ownership is blocked, making the controller look busy to the master device and making the master device look idle to the controller. The ownership is assigned to the master/controller pairs using an arbiter arrangement.

Abstract: A configurable and scaleable multi-bus platform for developing, testing and/or debugging prototype systems to be implemented in an integrated circuit includes a backplane providing multiple busses. Multiple system bus cards can be coupled to the backplane, and each of the system bus cards includes a system bus which is electrically coupled to at least one bus on the backplane. The system bus cards also include a bus infrastructure device providing support logic for operating the system bus. Daughter cards, containing master or slave devices for particular design configurations, are coupleable to the system bus cards in order to simulate a system bus which will be implemented in the integrated circuit. The backplane and system bus cards, as well as other components, can be easily reused in other projects for designing, testing and debugging other integrated circuits.

Abstract: A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter is not conducting a transaction. If the second device desires use of the bus, the slave arbiter sends a request to the master arbiter, which asserts an acknowledge signal for as long as the first device has ownership of the bus, and at least as long as a timeout of the first device. The master arbiter de-asserts its acknowledge signal when the first device ceases ownership of the bus. The slave arbiter is responsive to the de-assertion of the acknowledge signal to assert bus ownership to the second device. When the second device transaction is completed, its request signal is de-asserted to the master arbiter, causing the master arbiter to re-assert the acknowledge signal. Failure to receive a de-asserted acknowledge signal causes the slave arbiter to move to the next state.

Abstract: A pipeline processor having an exception program counter chain generates a return address in the exception program counter chain for an executing instruction. The return address is the point at which instruction execution should resume after an exception handler routine runs if the executing instruction incurs an exception. The return address is stored into a profiling register if and when the corresponding instruction completes execution. The profiling register is periodically sampled and a statistical profile is built of instructions executed in the processor by using the return addresses sampled. A sampled return address is identified as a branch delay instruction and included in the statistical profile if the sampled return address is that of a branch instruction which immediately precedes a branch delay instruction.

Abstract: Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event. The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode. A logic circuit associated with each processor responds to any debug event signal asserted by another processor and the failure of its associated processor to assert a debug event signal, to assert an external debug break signal to the associated processor and place the associated processor into the debug mode.

Abstract: A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter is not conducting a transaction. If the second device desires use of the bus, the slave arbiter sends a request to the master arbiter, which asserts an acknowledge signal for as long as the first device has ownership of the bus, and at least as long as a timeout of the first device. The master arbiter de-asserts its acknowledge signal when the first device ceases ownership of the bus. The slave arbiter is responsive to the de-assertion of the acknowledge signal to assert bus ownership to the second device. When the second device transaction is completed, its request signal is de-asserted to the master arbiter, causing the master arbiter to re-assert the acknowledge signal. Failure to receive a de-asserted acknowledge signal causes the slave arbiter to move to the next state.

Abstract: A system and method are presented for using spare gates to repair logic errors in a digital logic IC with a hierarchical physical design. According to the system and method, the spare gates are organized as scalable modules, consisting of varying numbers of identical sub-modules. The scalable modules are not part of the functional circuitry of the IC, but the spare gates within their sub-modules may be incorporated into faulty functional circuitry to correct the logic error. This is accomplished by altering the metalization layer of the IC to reconnect the spare gates, and does not require changing the physical layout (i.e., adding more pins, relocating gates, etc.) of the IC.

Abstract: An apparatus comprising a system configuration generator, a system builder and a simulation verification environment. The system configuration generator may be configured to generate a random system configuration file of a structurally variable and complex system. The system builder may be configured to build a system level netlist in response to the random system configuration file. The simulation verification environment may be configured to verify the structurally variable and complex system in response to the system level netlist. The simulation verification environment may be configured to provide automatic random verification of the system in response to the random system configuration file.

Abstract: A hardware description language (HDL) module is provided, which includes at least one input and output, including a clock input, a plurality of logic statements that define a function of the module, and a logic signal which is available within the module. The module further includes a synchronous assert check, which checks a state of the logic signal against a condition only during a predefined time window within a period of the clock input.

Abstract: A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.