Abstract: A processor is provided which performs relative addressing using the exception program counter. In one embodiment, a pipelined processor is provided with an exception program counter (EPC) register chain for tracking exception re-entry points in the instruction stream, and the instruction pipeline is provided with access to at least one of the registers in the register chain. The pipeline includes a fetch stage, a decode stage, and an execute stage. The exception PC register is identified by the decode stage as an operand in a memory access instruction for the execute stage to operate on. The execute stage then adds the contents of the exception PC register to the contents of a processor register or to a literal value to determine a target memory address.

Abstract: A value selection and printing apparatus includes a printing device having a printing wheel which is rotatable into a plurality of positions to present a corresponding plurality of value printing elements into a printing position; a value selecting device including a moveable first rack gear having a driven element thereon, a rigid guide shaft mounted within the printing device, a second rack gear mounted to be slidable on the guide shaft and having a driving element thereon in engagement with the driven element, wherein the second rack gear operatively engages the printing wheel so that rotation of the printing wheel occurs due to transmission of a moment of the first rack gear to the printing wheel via the second rack gear; and a substantially cylindrical security sleeve slidably disposed on the guide shaft and moveable in response to sliding movement of the second rack gear on the guide shaft wherein the guide shaft includes a weakened section such that at times when a force sufficient to disassociate the