Abstract: A table with drawers for displaying electronic devices is disclosed. The table may include a support beam and support panel within the table top for structural support. The table may include one or more drawers coupled to a carriage mechanism positioned rearward from the rear of the drawer. The carriage mechanism may be configured for moving the drawer from a first position to a second position.

Abstract: A display system for displaying an electronic device is disclosed. The display system may include a cup disposed in an aperture of a tray with a charging feature disposed therein. The charging feature may include a charging element for magnetically attaching to an electronic device and providing power to the electronic device.

Abstract: A display apparatus, such as a table, for display consumer products, such as electronic devices, is disclosed. The table may include a display cavity for displaying products. The display cavity may include a transparent glass panel defining a top portion thereof so as to allow consumers to view products housed within the display cavity. The table may include a lighting system configured to illuminate at least a portion of the display cavity. The table may also include a cooling system for maintaining or modifying the temperature within the display cavity. A rotatable display panel defining at least a portion of the bottom of display cavity may rotate from the bottom of the table to allow a user can access the products within the display cavity.

Abstract: A table having electrical ports for supplying power or data is disclosed. The table may include one or more port housings having one or more electrical ports disposed on a surface of the port housing. The port housing may be configured to rotate between a first position and a second position. In the first position, the one or more electrical ports may be concealed beneath the top surface of the table. In the second position, the one or more electrical port may be deployed above the top surface table. The table may include a motor coupled to an assembly for rotating the one or more port housings between the first position and the second position.

Abstract: A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.

Abstract: A frequency synthesizer system may generate two intermediate clock signals, each intermediate clock signal having the same nominal frequency (fN), the same cycle pattern with deterministic jitter, and the same corresponding average frequency (fA). However, the cycle pattern in one intermediate clock signal may be a specified number (N) of cycles out of phase with respect to the cycle pattern in the other intermediate clock signal. The cycle pattern may recur every 2N cycles in each intermediate clock signal. The duration of each cycle in each of the two intermediate clock signals is defined by fN and the deterministic jitter in the cycle pattern. An output clock signal may be generated by phase interpolating by two (2) the two intermediate clock signals, and dividing the resulting phase interpolated clock signal by N. The resulting output clock signal has an accurate frequency commensurate with fA/N, and is free of deterministic jitter.

Abstract: A communication system for transmitting and receiving a sequence of bits, and the methodology for transferring that sequence of bits are provided. The communication system includes a transmitting circuit and a receiving circuit. Within the transmitting circuit is a scrambler that comprises a shift register, an enable circuit, and an output circuit. The shift register temporarily stores n bits within the sequence of bits, and the enable circuit enables the shift register to store bits that arise only within the payload section of a frame. The output circuit includes a feedback, and several taps within the n stages to scramble logic values within the sequence of n bits output from the shift registers thus effectively preventing in most instances the sequence of bits from exceeding n number of the same logic value. Within the receiving circuit is a descrambler also having a shift register, an enable circuit, and an output circuit. The descrambler recompiles the scrambled data back to its original form.