Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: A speculum operable to be disposed within an ear of a subject may include a housing. The housing may include a light conducting element. A transmitted optical illumination may be conducted by total internal reflection via the light conducting element. The housing may include a lumen. The housing may be configured to allow a reflected optical illumination to propagate through the lumen. The speculum may include one or more coupling portions which couple the transmitted optical illumination from a light source to the light conducting element. The one or more coupling portions may be shaped as a conic section.

Abstract: Apparatus and methods for transceivers are provided herein. In a first aspect, an observation receiver is implemented to detect common-mode local oscillator (LO) leakage while the observation receiver performs other functions. In a second aspect, a transceiver is implemented with an LO leakage compensation circuit that compensates a transmitter for LO leakage using a digital filter, such as a Kalman filter, that combines differential LO leakage observations with common-mode LO leakage observations. In a third aspect, a transmitter includes multiple local loopback paths including a first loopback path after a variable gain amplifier (VGA) and a second loopback path before the VGA.

Abstract: In an embodiment, systems and methods for reviewing payments using artificial intelligence are provided. Training data is collected that includes payments made by insurance payors for claims received from medical providers. The payments may have been verified as correct and include metadata about the associated claim such as the medical service and whether the claim was in or out of network. The training data is used to train a model that predicts a payment amount for a claim from a medical provider for an insurance payor. When a payment is received, the model is used to predict the payment amount for the payment. The predicted amount is compared with the actual payment amount and is used to determine if the payment is anomalous. If the payment is anomalous, it is provided to an auditor who checks the payment for compliance with a contract between the payor and the provider.

Abstract: Systems, devices, and methods related to envelope regulated, digital predistortion (DPD) are provided. An example apparatus includes an envelope regulator circuit to process, based on a parameterized model, an input signal to generate an envelope regulated signal; a digital predistortion (DPD) actuator circuit to process the envelope regulated signal and the input signal based on DPD coefficients associated with a nonlinearity characteristic of a nonlinear component; and a DPD adaptation circuit to update the DPD coefficients based on a feedback signal indicative of an output of the nonlinear component.

Abstract: Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.

Abstract: Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.

Abstract: A method includes receiving information associated with a stimulus, the information associated with the stimulus comprising first information associated with a medical claim for services provided to a patient and second information associated with a provider that provided the services to the patient; and predicting, using an artificial intelligence engine, when an event will occur in response to the stimulus.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: An example device includes: a print engine including a fuser; an ambient temperature sensor; a memory storing a plurality of curves that relate, for given respective ambient temperatures, respective time periods for the fuser to heat to a fusing temperature, to respective factors associated with cooling of the fuser; and a processor The processor is to: detect a current ambient temperature using the ambient temperature sensor; select a curve, from the plurality of curves, using the current ambient temperature; determine a current factor associated with cooling of the fuser; and control the fuser to heat to the fusing temperature based on a respective time period determined from the curve and the current factor associated with cooling of the fuser.

Abstract: An example non-transitory machine-readable medium includes instructions that, when executed by a processor, cause the processor to receive a job to print multiple copies of a document, process a page of the document to obtain a processed page, initiate printing of the processed page at a printer, transmit via a network the processed page to network storage, and, when ready to print a subsequent copy of the page of the document, retrieve via the network the processed page from the network storage.

Abstract: A transmitter with a DC detection circuit that can control when a modulator of the transmitter is active. When data is being transmitted, a tone introduced by a mixer in the transmit path is hidden by the data signal and has minimal effect on the transmit path. However, when there is no data, the tone can cause undesirable noise. A modulator may move the tone or noise outside of the transmitter's bandwidth. As the data can hide the tone, the DSM may only be needed when there is a DC signal. By activating the DSM only when a DC signal is detected, the extra power introduced by the modulator can be reduced while eliminating in-band noise.

Abstract: Some embodiments herein describe a radio frequency power semiconductor device that include a first non-linear filter network for compensating for lower frequency noise of a power amplifier. The first non-linear filter network can include a plurality of infinite impulse response filters and corresponding corrective elements to correct for a non-linear portion of the power amplifier. The radio frequency power semiconductor device can further include a second non-linear filter network for compensating for broadband distortion. The second non-linear filter network can be connected in parallel to the first non-linear filter network. The broadband distortion can include digital predistortion and the narrowband distortion can include charge trapping effects. The first non-linear filter network can comprise Laguerre filters. The second non-linear filter network can comprise general memory polynomial filters.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: A radio timing controller equipped with one or more sequence controllers is disclosed. Sequence controllers enable high degree of programmability of the radio timing controller, e.g., in terms of the number of general purpose input/outputs (GPIOs), mapping of GPIOs to specific radio controls, setting of the radio control output states, timing to sequence events at radio symbol boundaries, etc.

Abstract: Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.