Abstract: A computer-implemented method operating on a first aircraft and performed by one or more processors collects sensor data and aircraft performance data generated by the first aircraft during flight. The method pre-processes the sensor and performance data generating a context with respect to the first aircraft. The method transmits the pre-processed sensor data and first aircraft performance data to a set of aircraft within a region of the first aircraft. The method receives pre-processed sensor data and aircraft performance data from the set of aircraft within the region of the first aircraft. The method processes the received pre-processed sensor and performance data from the set of aircraft, and the method generates alerts associated with adverse conditions determined based on the analysis of the pre-processed sensor data and performance data received from the set of aircraft in the context of the performance data of the first aircraft.

Abstract: An approach for managing and minimized failure of one or more devices in a computerized cluster and/or vehicle infrastructure is disclosed. The proactive approach for mitigating such black swan events as it relate to hardware failures (e.g., servers, network, vehicle systems/architecture, etc.). The approach would proactively inactivate “suspect” components (i.e., components that are completely functional in multiple systems) based on component vintage data from systems where components have failed or malfunctioned. A dedicated service is actively updating suspect components and their respective vintages spread across various systems. Furthermore, the approach backups components using different vintages are effectively utilized to avoid complete system failure.

Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.

Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.

Abstract: An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Abstract: A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conductive bond pad in the reference direction, wherein the patterned support/interface layer includes a hole and a trench, wherein the hole is directly above the electrically conductive bond pad, and wherein the trench is not filled by any electrically conductive material; and (d) an electrically conductive solder bump filling the hole and electrically coupled to the electrically conductive bond pad.

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.

Abstract: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.

Abstract: The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).

Abstract: A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line site for alignment of the dicing blade. A plurality of rectangular elements is situated about the periphery of the alignment mark and populated with via bar structures that are interconnected at each level of the wafer, and laid in a serpentine fashion throughout each element to expose more of the via bar structure surface area to propagating cracks. The rectangular elements are formed of different sizes to expose more surface area to propagating cracks. A plurality of square, metal-level structures is formed in the area between the cross-shaped structure and the peripherally placed, rectangular elements.

Abstract: A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.

Abstract: An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Abstract: A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.

Abstract: A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.

Abstract: A semiconductor structure and method for chip dicing. The method includes (a) providing a semiconductor substrate and (b) forming first and second device regions in and at top of the substrate. The first and second device regions are separated by a semiconductor border region of the substrate. The method further includes (c) forming N interconnect layers, in turn, directly above the semiconductor border region and the first and second device regions. N is a positive integer greater than one. Each of the N interconnect layers includes an etchable portion directly above the semiconductor border region. The etchable portions of the N interconnect layers form a continuous etchable block directly above the semiconductor border region. The method further includes (d) removing the continuous etchable block by etching, and (e) cutting with a laser through the semiconductor border region via an empty space of the removed continuous etchable block.

Abstract: A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.

Abstract: An Integrated Circuit (IC) chip with fused circuits and method of making the IC. Fuses in an upper wiring layer are formed using a multi-tone mask to define rounded bottom corners on the fuses, while wiring in the upper wiring layer maintain a rectangular cross-section.

Abstract: A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.