SOLDER WALL STRUCTURE IN FLIP-CHIP TECHNOLOGIES
A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
1. Technical Field
The present invention relates to flip-chip technologies, and more specifically, to a solder wall structure in flip-chip technologies.
2. Related Art
In typical flip-chip technologies, solder bumps are formed on top of a chip to help bond the chip to a ceramic substrate. These solder bumps may be corroded by carbon dioxide and water vapor of the surrounding ambient environment. Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient.
SUMMARY OF THE INVENTIONThe present invention provides a semiconductor structure, comprising (a) a first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
The present invention also provides a semiconductor fabrication method, comprising providing a first semiconductor chip; forming N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and forming a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
The present invention also provides a semiconductor structure, comprising (a) a first semiconductor chip comprising a crack stop on a perimeter of the first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps, and such that the first solder wall is overlapping the crack stop; and (d) a module substrate coupled to the first solder wall and the N solder bumps
Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient.
BRIEF DESCRIPTION OF THE DRAWINGS
In one embodiment, the top interconnect layer 106a of the semiconductor chip 102 includes (i) a dielectric layer 110a, (ii) an electrically conducting line 120a (comprising copper (Cu) in one embodiment) embedded in the dielectric layer 110a, and (iii) a metal region 122a (comprising Cu in one embodiment) embedded in the dielectric layer 110a. Similarly, the interconnect layers 106b, 106c, and 106d comprise dielectric layers 110b, 110c, and 110d, electrically conducting lines 120b, 120c, and 120d (comprising Cu in one embodiment), and metal regions 122b, 122c, and 122d (comprising Cu in one embodiment), respectively. In one embodiment, the metal regions 122a, 122b, 122c, and 122d run on a perimeter of the semiconductor chip 102 and form a crack stop 122 surrounding the semiconductor chip 102. In one embodiment, the crack stop 122 is to prevent cracking from propagating from the dicing channel region 104 to the semiconductor chip 102 during a chip dicing process. It should be noted that from
Next, with reference to
Next, in one embodiment, a bond pad 130 (comprising aluminum (Al) in one embodiment) is formed on top of the Cu line 120a and the dielectric layer 110a such that the Al bond pad 130 is electrically coupled to the Cu line 120a. In one embodiment, a wall base 132 (comprising Al in one embodiment) is formed on top of the crack stop 122 and the dielectric layer 110a such that the Al wall base 132 is in direct physical contact with the crack stop 122. Illustratively, the Al bond pad 130 and the Al wall base 132 can be simultaneously formed by (a) forming an Al layer (not shown) on the entire structure 100, and then (b) directionally and selectively etching back the Al layer stopping at the dielectric layer 110a. The directional and selective etching in step (b) may be performed using a traditional lithographic and etching process such that what remains of the Al layer after the etching are the Al bond pad 130 and the Al wall base 132 (as shown in
Next, with reference to
In one embodiment, the patterned support/interface layer 140 is formed using a photosensitive method. More specifically, the patterned support/interface layer 140 is formed by (i) spin-applying a polyimide film (not shown) on the structure 100 of
Next, with reference to
Next, with reference to
Next, in one embodiment, a solder bump 170 (comprising a mixture of lead (Pb) and tin (Sn) in one embodiment) and a solder wall 172 (comprising a mixture of Pb and Sn in one embodiment) are simultaneously formed in the hole 142,162 and the trench 146,166, respectively, by, illustratively, electroplating. More specifically, in one embodiment, the structure 100 is submerged in a solution (not shown) containing tin and lead ions. The BLM film 150 is electrically coupled to the cathode of an external dc (direct current) power supply (not shown), while the solution is electrically coupled to the anode of the dc supply. Under the electric field created in the solution by the dc power supply, tin and lead ions in the solution arrive at the exposed surfaces 164 and 168 of the BLM film 150 and deposit there forming the solder bump 170 and the solder wall 172, respectively, as shown in
Next, in one embodiment, the patterned photo-resist layer 160 and portions of the BLM film 150 (that are not protected by the solder bump 170 and the solder wall 172) are removed by wet etching, RIE etching, or electro-etch, resulting in the solder bump 170, the solder wall 172, and BLM regions 150 of the structure 100 of
Next, in one embodiment, the solder bump 170 and the solder wall 172 of
Next, in one embodiment, the chip dicing process is performed wherein a blade (not shown) can be used to cut through the dicing channel region 104, resulting in the separated semiconductor chip 102 in
Next, with reference to
In one embodiment, other chips (not shown, but similar to the chip 102 of
In summary, after the chip 102 is bonded to the ceramic module substrate 180, the solder bumps 170 of the chip 102 are isolated from carbon dioxide and water vapor of the surrounding ambient environment by the chip 102, the ceramic module substrate 180, and the solder wall 172.
While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims
1. A semiconductor structure, comprising:
- (a) a first semiconductor chip;
- (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and
- (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
2. The structure of claim 1, further comprising a module substrate coupled to the first solder wall and the N solder bumps,
- wherein the module substrate includes N substrate bump pads such that the N solder bumps are electrically coupled one-to-one to the N substrate bump pads, and
- wherein the N solder bumps are isolated from a surrounding ambient environment by the first semiconductor chip, the first solder wall, and the module substrate.
3. The structure of claim 2, further comprising:
- (i) a second semiconductor chip,
- (ii) M solder bumps in direct physical contact with the second semiconductor chip, wherein M is a positive integer, and
- (iii) a second solder wall on a perimeter of the second semiconductor chip such that the second solder wall forms a closed loop surrounding the M solder bumps,
- wherein the module substrate further includes M substrate bump pads such that the M solder bumps are electrically coupled one-to-one to the M substrate bump pads of the module substrate, and wherein the M solder bumps are isolated from the surrounding ambient environment by the second semiconductor chip, the second solder wall, and the module substrate.
4. The structure of claim 2, wherein the module substrate comprises ceramic.
5. The structure of claim 1,
- wherein the first semiconductor chip comprises a crack stop on a perimeter of the first semiconductor chip, and
- wherein the first solder wall is overlapping the crack stop.
6. The structure of claim 1, wherein the first solder wall and the N solder bumps comprises a same material.
7. The structure of claim 6, wherein the same material comprises a mixture of tin and lead.
8. The structure of claim 1, wherein the first semiconductor chip comprises N bump limiting metallurgy regions being in direct physical contact with the N solder bumps.
9. A semiconductor fabrication method, comprising:
- providing a first semiconductor chip;
- forming N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and
- forming a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
10. The method of claim 9, wherein said forming the N solder bumps and said forming the first solder wall are performed simultaneously.
11. The method of claim 9, wherein said forming the N solder bumps and said forming the first solder wall are performed by using electroplating.
12. The method of claim 9, further comprising bonding the first solder wall and the N solder bumps to a module substrate,
- wherein the module substrate includes N substrate bump pads such that the N solder bumps are electrically coupled one-to-one to the N substrate bump pads, and
- wherein the N solder bumps are isolated from a surrounding ambient environment by the first semiconductor chip, the first solder wall, and the module substrate.
13. The structure of claim 12, further comprising:
- providing (i) a second semiconductor chip, (ii) M solder bumps in direct physical contact with the second semiconductor chip, wherein M is a positive integer, and (iii) a second solder wall on a perimeter of the second semiconductor chip such that the second solder wall forms a closed loop surrounding the M solder bumps; and
- bonding the second solder wall and the M solder bumps to the module substrate, such that the M solder bumps are isolated from the surrounding ambient environment by the second semiconductor chip, the second solder wall, and the module substrate.
14. The method of claim 9,
- wherein the first semiconductor chip comprises a crack stop on a perimeter of the first semiconductor chip, and
- wherein the first solder wall is overlapping the crack stop.
15. The method of claim 9, wherein the first solder wall and the N solder bumps comprises a same material.
16. The method of claim 15, wherein the same material comprises a mixture of tin and lead.
17. The method of claim 9, wherein the first semiconductor chip comprises N bump limiting metallurgy regions being in direct physical contact with the N solder bumps.
18. A semiconductor structure, comprising:
- (a) a first semiconductor chip comprising a crack stop on a perimeter of the first semiconductor chip;
- (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer;
- (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps, and such that the first solder wall is overlapping the crack stop; and
- (d) a module substrate coupled to the first solder wall and the N solder bumps.
19. The structure of claim 18, wherein the module substrate comprises ceramic.
20. The structure of claim 18, wherein the first solder wall and the N solder bumps comprises a mixture of tin and lead.
Type: Application
Filed: Feb 1, 2006
Publication Date: Aug 2, 2007
Patent Grant number: 7547576
Inventors: Timothy Daubenspeck (Colchester, VT), Jeffrey Gambino (Westford, VT), Christopher Muzzy (Burlington, VT), Wolfgang Sauter (Richmond, VT)
Application Number: 11/275,867
International Classification: H01L 23/48 (20060101);