Abstract: An advanced connector assembly enabled to receive and distribute power signals. In one embodiment, the connector comprises a multi-port modular jack, and incorporates a PSE controller board disposed in the rear portion of the connector assembly, e.g., outside the connector housing. The PSE controller board controls the power to a powered device and may be adapted to, for example, distinguish whether the device is a short circuit or a network interface card, guarantee the supply of power to selected ports, and prevent cables from transmitting abnormal power. Heat removal features are also optionally utilized to effectively dissipate heat produced by the electronic or signal conditioning components utilized on said multi-port modular jack. In some embodiments, the PSE controller board is also optionally made removable from the jack housing.

Abstract: A structure and a manufacturing method providing improved coplanarity accommodation and heat dissipation in a multi-chip module. One of the components in a multi-chip module (MCM) is provided with a recess formed in its respective top surface; and a film is applied so as to cover the top surfaces of the components and so that any excess film can enter into the recess. The recess is preferably a peripheral groove. Then when molding material is injected, it may surround and seal the side surfaces of the components, while not substantially covering the top surfaces that are covered by the film. Since the recess receives any excess film material that may be present, it may prevent such excess film material from covering the respective side surfaces of the corresponding component and creating a void between the component and the molding material.

Abstract: A structure and a manufacturing method providing improved coplanarity accommodation and heat dissipation in a multi-chip module. One of the components in a multi-chip module (MCM) is provided with a recess formed in its respective top surface; and a film is applied so as to cover the top surfaces of the components and so that any excess film can enter into the recess. The recess is preferably a peripheral groove. Then when molding material is injected, it may surround and seal the side surfaces of the components, while not substantially covering the top surfaces that are covered by the film. Since the recess receives any excess film material that may be present, it may prevent such excess film material from covering the respective side surfaces of the corresponding component and creating a void between the component and the molding material.

Abstract: Connector apparatus and methods providing for “keep-out” functionality against improperly sized plugs or inserts are disclosed. In one embodiment the invention discloses a connector assembly incorporating an integrated keep-out feature associated with the housing. In one variant, the connector assembly comprises a modular jack connector, and the keep-out feature(s) is/are formed substantially within one or more the sidewall(s) of the housing, thereby simplifying its assembly and reducing its cost, as well as conserving on connector interior space. In another embodiment, the keep-out feature comprises an element disposed substantially within a plane parallel to the front face of the connector. Methods for manufacturing and using connectors with integrated keep-out features are also disclosed.

Abstract: A wire-less inductive device and methods of manufacturing and use are disclosed. In one embodiment, the inductive device comprises a plurality of through-hole vias which act to replace windings disposed around a magnetically permeable core. In another embodiment, the inductive device comprises a plurality of connection elements disposed or formed within channels which act as windings disposed around a magnetically permeable core. In a second aspect of the invention, a method of manufacturing the aforementioned inductive devices is disclosed. In a third aspect of the invention, an electronics assembly and circuit comprising the wire-less inductive devices are disclosed.

Abstract: A testing apparatus and method for testing a semiconductor device, and more particularly a test arrangement for measuring a guaranteed power loss of a semiconductor module, not requiring the module to have on-board decoupling capacitors for the power loss test. The conventional pogo-pin array and test socket are replaced by a novel low cost anisotropic conductive elastomer and a low cost socket, the conductive polymer providing electrical communication between the socket and the module under test.

Abstract: The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

Abstract: A multi-chip module that includes a conductive element to serve as an electrical connector for electrically connecting respective electrical contacts of at least two power semiconductor devices and serving as an output connector. The conductive element improving heat transfer from the power semiconductor devices through the top of the module.

Abstract: A multi-chip module that includes a conductive element to serve as an electrical connector for electrically connecting respective electrical contacts of at least two power semiconductor devices and serving as an output connector. The conductive element improving heat transfer from the power semiconductor devices through the top of the module.

Abstract: A microelectronic device structure includes a diamond-containing substrate, and a metallic interlayer affixed to the diamond. The interlayer is made of a metal such as copper, silver, or gold, has a thickness of from about 0.003 inch to about 0.009 inch, and has an upper surface. A microelectronic device die is affixed to the upper surface of the metallic interlayer. The material of construction and thickness of the metallic interlayer are selected such that a coefficient of thermal expansion at the upper surface of the metallic interlayer is greater than a coefficient of thermal expansion of the die of the microelectronic device by up to about 3 parts per million per degree Centigrade.