Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

Abstract: An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such that a plurality of bits can be determined during a single trial step; and during a second phase of the analog to digital conversion the conversion engines work independently; and the controller receives the outputs of at least one of the conversion engines and processes them to provide an output word.

Abstract: A method of operating a digital to analog converter comprising the steps of operating the converter in a first mode to obtain a first conversion result, operating the converter in a correction mode in which one or more correction conversions are made, and wherein each correction conversion takes the result of a preceding result as a valid starting point.

Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. Reducing power consumption of a SAR system can be readily accomplished by reducing comparator supply voltage. For a SAR converter architecture using a CAPDAC array or CAPDAC (capacitor array DAC), fairly large variations in comparator input voltage can be expected under these circumstances.

Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.

Abstract: An ADC (1) of balanced architecture for determining a digital word corresponding to a sampled voltage of an input signal from an input line (33) comprises a first capacitor circuit (2) comprising a most significant capacitor array (4) and a least significant capacitor array (5) which are capacitively coupled by a coupling capacitor Cc1. A second capacitor circuit (29) coupled to ground balances the first capacitor circuit (2). A differential comparator 27 compares the voltage on the first capacitor circuit (2) with that on the second capacitor circuit (29).

Abstract: Gain correction for a digital filter is accomplished by multiplying each data value by a coefficient representing the impulse response of the filter to form a convolution of the data values; accumulating the sum of the product of each multiplication to obtain a complete convolution; determining the difference between the positive full scale output and the negative full scale output of the filter; combining this difference with the ideal full scale output value to obtain the gain error factor; dividing the gain error factor by the full scale ideal value to obtain the gain correction factor; multiplying the negated accumulated sum of the product of each multiplication by the gain correction factor to obtain the gain error adjustment factor and combining the gain error adjustment factor with the accumulated sum to compensate for gain errors in the filter output.