Patents by Inventor Christopher Putnam

Christopher Putnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9121137
    Abstract: A dispersible article and methods of making the same. The article has a web of fibers and a dried binder in contact with the fibers. The web of fibers has a basis weight of from about 10 gsm to about 150 gsm. The dried binder has a polyfunctional aldehyde and a primary polymer. The primary polymer has at least one functional group that is reactive with the fibers or the polyfunctional aldehyde. The fibers have at least one functional group that is reactive with the polyfunctional aldehyde or the primary polymer. The article has a cross direction wet tensile strength after 15 minutes of aqueous saturation that is at least about 30% of an initial cross direction wet tensile strength. The article is flushable.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: September 1, 2015
    Assignees: SELLARS ABSORBENT MATERIALS, INC., SOLENIS TECHNOLOGIES, L.P.
    Inventors: Helen Viazmensky, Martyn Reginald Searle Davis, Richard J. Riehle, Marc Christopher Putnam, Joel E. Goldstein, Jerry Ballas, Doeung David Choi
  • Publication number: 20140311696
    Abstract: A dispersible article and methods of making the same. The article has a web of fibers and a dried binder in contact with the fibers. The web of fibers has a basis weight of from about 10 gsm to about 150 gsm. The dried binder has a polyfunctional aldehyde and a primary polymer. The primary polymer has at least one functional group that is reactive with the fibers or the polyfunctional aldehyde. The fibers have at least one functional group that is reactive with the polyfunctional aldehyde or the primary polymer. The article has a cross direction wet tensile strength after 15 minutes of aqueous saturation that is at least about 30% of an initial cross direction wet tensile strength. The article is flushable.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 23, 2014
    Applicants: Sellars Absorbent Materials, Inc., Hercules Incorporated
    Inventors: Helen Viazmensky, Martyn Reginald Searle Davis, Richard J. Riehle, Marc Christopher Putnam, Joel E. Goldstein, Jerry Ballas, Doeung David Choi
  • Patent number: 8719185
    Abstract: An energy tracking and reporting system can receive data inputs from multiple sources regarding one or more properties. A central database receives the information and correlates the information for numerous outputs. Information received by the central database can include, for example, property location, property size, property type and property use. Also, occupancy information, energy sources, utilities servicing the property, weather, ISO, environmental guidelines, and the traded or other standard price for the utilities can be stored. The system can calculate a number of factors from the data and return values to the central database. The system can track data trends and store additional information for budgeting, user reporting and certification compliance reporting. Modules can analyze the market rates, calculate efficiency benchmarks, analyze the data stored on the central database and provide the user with multiple tables and charts analyzing all of the factors that tie into energy usage.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 6, 2014
    Assignee: MC Energy, Inc.
    Inventors: Margaret M. Carey, Douglas L. Pfeister, Christopher Putnam
  • Publication number: 20110161251
    Abstract: An energy tracking and reporting system can receive data inputs from multiple sources regarding one or more properties. A central database receives the information and correlates the information for numerous outputs. Information received by the central database can include, for example, property location, property size, property type and property use. Also, occupancy information, energy sources, utilities servicing the property, weather, ISO, environmental guidelines, and the traded or other standard price for the utilities can be stored. The system can calculate a number of factors from the data and return values to the central database. The system can track data trends and store additional information for budgeting, user reporting and certification compliance reporting. Modules can analyze the market rates, calculate efficiency benchmarks, analyze the data stored on the central database and provide the user with multiple tables and charts analyzing all of the factors that tie into energy usage.
    Type: Application
    Filed: September 28, 2010
    Publication date: June 30, 2011
    Inventors: Margaret M. Carey, Douglas L. Pfeister, Christopher Putnam
  • Patent number: 7818270
    Abstract: An energy tracking and reporting system can receive data inputs from multiple sources regarding one or more properties. A central database receives the information and correlates the information for numerous outputs. Information received by the central database can include, for example, property location, property size, property type and property use. Also, occupancy information, energy sources, utilities servicing the property, weather, ISO, environmental guidelines, and the traded or other standard price for the utilities can be stored. The system can calculate a number of factors from the data and return values to the central database. The system can track data trends and store additional information for budgeting, user reporting and certification compliance reporting. Modules can analyze the market rates, calculate efficiency benchmarks, analyze the data stored on the central database and provide the user with multiple tables and charts analyzing all of the factors that tie into energy usage.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: October 19, 2010
    Inventors: Margaret M. Carey, Douglas L. Pfeister, Christopher Putnam
  • Publication number: 20080108185
    Abstract: An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
    Type: Application
    Filed: December 20, 2007
    Publication date: May 8, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mahmoud Mousa, Christopher Putnam
  • Publication number: 20080050880
    Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 28, 2008
    Applicant: International Business Machines Corporation
    Inventors: Michel Abou-Khalil, Robert Gauthier, Hongmei Li, Junjun Li, Souvick Mitra, Christopher Putnam
  • Publication number: 20070262345
    Abstract: A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
    Type: Application
    Filed: July 23, 2007
    Publication date: November 15, 2007
    Inventors: Robert Gauthier, Junjun Li, Souvick Mitra, Mahmoud Mousa, Christopher Putnam
  • Publication number: 20070253126
    Abstract: Electrostatic discharge (ESD) protection device and process for protecting a conventional FET. The device includes at least one FET body forming a resistance, and a triggering circuit coupled to a protection FET and the resistance. The resistance raises a voltage of the at least one body, such that the protection FET is triggered at a voltage lower than the conventional FET.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 1, 2007
    Inventors: Robert Gauthier, Jr., Junjun Li, Souvick Mitra, Christopher Putnam
  • Publication number: 20070170512
    Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 26, 2007
    Inventors: Robert Gauthier, Jr., Junjun Li, Souvick Mitra, Mahmoud Mousa, Christopher Putnam
  • Publication number: 20070097570
    Abstract: Method and device for protecting against electrostatic discharge. The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network. The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage.
    Type: Application
    Filed: December 21, 2006
    Publication date: May 3, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiran CHATTY, Robert GAUTHIER, Mahmoud MOUSA, Mujahid MUHAMMAD, Christopher PUTNAM
  • Publication number: 20070053120
    Abstract: An apparatus for protecting an integrated circuit from an electrostatic discharge (ESD) event includes a multiple stage triggering network configured between a pair of power rails, and a power clamp coupled to the multiple stage triggering network, the power clamp configured to discharge current from the ESD event. The multiple stage triggering network has a first control path and a second control path configured to individually control activation of the power clamp.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 8, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Gauthier, Junjun Li, Souvick Mitra, Christopher Putnam
  • Publication number: 20060226491
    Abstract: An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with an active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 12, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Gauthier, Mahmoud Mousa, Christopher Putnam
  • Publication number: 20060157799
    Abstract: A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.
    Type: Application
    Filed: January 17, 2005
    Publication date: July 20, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiran Chatty, Robert Gauthier, Terence Hook, Christopher Putnam, Mujahid Muhammad
  • Publication number: 20060161450
    Abstract: An energy tracking and reporting system can receive data inputs from multiple sources regarding one or more properties. A central database receives the information and correlates the information for numerous outputs. Information received by the central database can include, for example, property location, property size, property type and property use. Also, occupancy information, energy sources, utilities servicing the property, weather, ISO, environmental guidelines, and the traded or other standard price for the utilities can be stored. The system can calculate a number of factors from the data and return values to the central database. The system can track data trends and store additional information for budgeting, user reporting and certification compliance reporting. Modules can analyze the market rates, calculate efficiency benchmarks, analyze the data stored on the central database and provide the user with multiple tables and charts analyzing all of the factors that tie into energy usage.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 20, 2006
    Applicant: MC Energy, Inc.
    Inventors: Margaret Carey, Douglas Pfeister, Christopher Putnam
  • Publication number: 20060072267
    Abstract: A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiran Chatty, Robert Gauthier, Mahmoud Mousa, Mujahid Muhammad, Christopher Putnam
  • Publication number: 20060043571
    Abstract: An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
    Type: Application
    Filed: August 30, 2004
    Publication date: March 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mahmoud Mousa, Christopher Putnam
  • Publication number: 20050272195
    Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.
    Type: Application
    Filed: July 21, 2005
    Publication date: December 8, 2005
    Inventors: Andres Bryant, William Clark, David Fried, Mark Jaffe, Edward Nowak, John Pekarik, Christopher Putnam
  • Publication number: 20050227418
    Abstract: A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiran Chatty, Robert Gauthier, Mujahid Muhammad, Christopher Putnam
  • Publication number: 20050224882
    Abstract: An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiran Chatty, Robert Gauthier, Mujahid Muhammad, Christopher Putnam