Abstract: A CAD/GIS system that dynamically updates planar topologies through incremental updating techniques. Rather than batch processing all of the changes to every geometrical feature in a given site map, the changes are made in incremental fashion and only enclosures or faces/parcels that are affected by changes are updated.

Abstract: A CAD/GIS system that automatically generates faces within land site maps, by sliding or rotating line segments between boundaries given start points and other attributes. As the attributes are entered into the system, faces are automatically generated based on those attributes, which eases creation of lots within subdivisions.

Abstract: A CAD/GIS system that automatically discovers hierarchical relationships between root faces/parcels, smaller faces/parcels, and other defined areas of land. As the definitions are entered into the system, hierarchical relationships are created by the system to ease data management functions.

Abstract: The present invention provides for disconnecting a capacitive path from a device when the capacitive path is no longer needed. Disconnecting a capacitive path when it is no longer needed is beneficial because the existence of a capacitive path limits the speed of the protected device. The device is separated from the capacitive path as a function of the current between the IO pad and a control device.

Abstract: An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An ESD protection circuit according to claim 7, wherein said RC network includes one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).

Abstract: A method, apparatus, and article of manufacture provide the ability to manipulate a drawing surface in a CAD/GIS computer application. A drawing surface is displayed in a CAD/GIS application followed by the performance of a surface edit operation on the drawing surface. The surface edit operation is stored/saved as an atomic property in a list of surface edit operations. The list of surface edit operations is displayed in a graphical user interface (GUI). Each surface edit operation may be independently toggled on/off in the GUI and such toggling is reflected in the CAD/GIS application by displaying an effect of executing the surface edit operation if toggled on and displaying the drawing surface without execution of the surface edit operation if toggled off.

Abstract: A method and apparatus for protection against electrostatic discharge (ESD) with improved latch-up robustness featuring a silicide blocked p-type field effect transistor is disclosed. The transistor has a snapback voltage that is less than the breakdown voltage of its gate oxide. The transistor is part of an integrated circuit and coupled to an I/O pad having no n-diffusions connected directly to it. A given integrated circuit may employ one or more the transistors configured in accordance with the invention that are associated with one or more I/O pads within the integrated circuit.

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.