Patents by Inventor Christopher R. Hatem

Christopher R. Hatem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11315790
    Abstract: A method may include providing a substrate in a plasma chamber, the substrate comprising a monocrystalline semiconductor, having an upper surface. The method may include initiating a plasma in the plasma chamber, the plasma comprising an amorphizing ion species, and applying a pulse routine to the substrate, the pulse routine comprising a plurality of extraction voltage pulses, wherein a plurality of ion pulses are directed to the substrate, and wherein an ion dose per pulse is greater than a threshold for low dose amorphization.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: April 26, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Supakit Charnvanichborikarn, Christopher R. Hatem
  • Publication number: 20210265139
    Abstract: Provided herein are approaches for controlling radicals in proximity to a wafer. In some embodiments, a system may include a radical source operable to generate radicals in proximity to the wafer, and a filter positioned between the radical source and the wafer, wherein the filter includes a first plate operable to control radicals generated by the radical source. The system may further include an ion source operable to deliver an ion beam to the wafer, wherein the ion beam passes outside the filter.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Applicant: Applied Materials, Inc.
    Inventor: Christopher R. Hatem
  • Publication number: 20210118681
    Abstract: A method may include providing a substrate in a plasma chamber, the substrate comprising a monocrystalline semiconductor, having an upper surface. The method may include initiating a plasma in the plasma chamber, the plasma comprising an amorphizing ion species, and applying a pulse routine to the substrate, the pulse routine comprising a plurality of extraction voltage pulses, wherein a plurality of ion pulses are directed to the substrate, and wherein an ion dose per pulse is greater than a threshold for low dose amorphization.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Applicant: Applied Materials, Inc.
    Inventors: SUPAKIT CHARNVANICHBORIKARN, CHRISTOPHER R. HATEM
  • Publication number: 20200411342
    Abstract: A beamline architecture including a wafer handling chamber, a load-lock coupled to the wafer handling chamber for facilitating transfer of workpieces between an atmospheric environment and the wafer handling chamber, a plasma chamber coupled to the wafer handling chamber and containing a plasma source for performing at least one of a plasma pre-clean process, a plasma enhanced chemical vapor deposition process, a plasma annealing process, a pre-heating process, and an etching process on workpieces, a process chamber coupled to the wafer handling chamber and adapted to perform an ion implantation process on workpieces, and a valve disposed between the wafer handling chamber and the plasma chamber for sealing the plasma chamber from the wafer handling chamber and the process chamber, wherein a pressure within the plasma chamber and a pressure within the process chamber can be varied independently of one another.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: APPLIED Materials, Inc.
    Inventors: Christopher R. Hatem, Christopher A. Rowland, Joseph C. Olson
  • Publication number: 20200152466
    Abstract: A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Piero Sferlazzo, Roger Fish, Dale K. Stone
  • Patent number: 10541137
    Abstract: A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 21, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Piero Sferlazzo, Roger Fish, Dale K. Stone
  • Publication number: 20190371608
    Abstract: A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Piero Sferlazzo, Roger Fish, Dale K. Stone
  • Publication number: 20180240670
    Abstract: A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 23, 2018
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Christopher A. Rowland
  • Patent number: 9953835
    Abstract: A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 24, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Christopher A. Rowland
  • Publication number: 20170178908
    Abstract: A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300 ° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature.
    Type: Application
    Filed: January 23, 2017
    Publication date: June 22, 2017
    Inventors: Christopher R. Hatem, Christopher A. Rowland
  • Patent number: 9589802
    Abstract: A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: March 7, 2017
    Assignee: Varian Semuconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Christopher A. Rowland
  • Patent number: 9576819
    Abstract: A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: February 21, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Kevin Jones, Aaron Lind
  • Patent number: 9240350
    Abstract: A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: January 19, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Christopher R. Hatem, George D. Papasouliotis
  • Patent number: 9236257
    Abstract: A method for processing a substrate includes providing a set of patterned structures separated by a first gap on the substrate and directing first implanting ions to the substrate at a first ion energy, where the first implanting ions are effective to impact the substrate in regions defined by the first gap. The method also includes directing depositing ions to the substrate where the second ions are effective to deposit material on at least a portion of the set of patterned structures to form expanded patterned structures, where the expanded patterned structures are characterized by a second gap smaller than the first gap. The method further includes directing second implanting ions to the substrate at a second ion energy, where the second implanting ions effective to impact the substrate in regions defined by the second gap, the second ion energy comprising a higher ion energy than the first ion energy.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 12, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Anthony Renau, John J. Hautala, Ludovic Godet
  • Publication number: 20150364325
    Abstract: A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 17, 2015
    Inventors: Christopher R. Hatem, Benjamin Colombeau, Kevin Jones, Aaron Lind
  • Patent number: 9062367
    Abstract: A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 23, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Christopher R. Hatem, Ludovic Godet, Louis Steen, Deepak A. Ramappa
  • Patent number: 9024273
    Abstract: An apparatus that generates molecular ions and methods to generate molecular ions are disclosed. At least a first species is ionized in an ion source. The first species ions and/or first species combine to form molecular ions. These molecular ions may be transported to a second chamber, which may be an arc chamber or diffusion chamber, and are extracted. The molecular ions may have a larger atomic mass than the first species or first species ions. A second species also may be ionized with the first species to form molecular ions. In one instance, the first and second species are both molecules.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: May 5, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Svetlana Radovanov, Christopher R. Hatem
  • Patent number: 8969181
    Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 3, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Morgan D. Evans, Christopher R. Hatem
  • Patent number: 8742373
    Abstract: A plasma is formed from one or more gases in a plasma chamber using at least a first power and a second power. A first ion species is generated at said first power and a second ion species is generated at said second power. In one embodiment, the first ion species and second ion species are implanted into a workpiece at two different energies using at least a first bias voltage and a second bias voltage. This may enable implantation to two different depths. These ion species may be atomic ions or molecular ions. The molecular ions may be larger than the gases used to form the plasma.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: June 3, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Svetlana Radovanov, Ludovic Godet, Christopher R. Hatem
  • Patent number: 8465909
    Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: June 18, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Helen L. Maynard, Benjamin B. Riordon, Christopher R. Hatem, Deepak Ramappa