Patents by Inventor Christopher R. Hatem
Christopher R. Hatem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8969181Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.Type: GrantFiled: April 5, 2012Date of Patent: March 3, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Morgan D. Evans, Christopher R. Hatem
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Patent number: 8742373Abstract: A plasma is formed from one or more gases in a plasma chamber using at least a first power and a second power. A first ion species is generated at said first power and a second ion species is generated at said second power. In one embodiment, the first ion species and second ion species are implanted into a workpiece at two different energies using at least a first bias voltage and a second bias voltage. This may enable implantation to two different depths. These ion species may be atomic ions or molecular ions. The molecular ions may be larger than the gases used to form the plasma.Type: GrantFiled: December 10, 2010Date of Patent: June 3, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Svetlana Radovanov, Ludovic Godet, Christopher R. Hatem
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Patent number: 8465909Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.Type: GrantFiled: November 1, 2010Date of Patent: June 18, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Nicholas P. T. Bateman, Helen L. Maynard, Benjamin B. Riordon, Christopher R. Hatem, Deepak Ramappa
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Patent number: 8460569Abstract: A method of patterning a substrate, comprises providing a set of patterned features on the substrate, exposing the set of patterned features to a dose of ions incident on the substrate over multiple angles, and selectively etching exposed portions of the patterned features.Type: GrantFiled: April 7, 2011Date of Patent: June 11, 2013Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Christopher R. Hatem, Patrick M. Martin, Timothy J. Miller
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Publication number: 20130064989Abstract: A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.Type: ApplicationFiled: September 10, 2012Publication date: March 14, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Ludovic Godet, Louis Steen, Deepak A. Ramappa
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Publication number: 20120295444Abstract: A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.Type: ApplicationFiled: May 15, 2012Publication date: November 22, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, Christopher R. Hatem, George D. Papasouliotis
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Publication number: 20120258600Abstract: A method of patterning a substrate, comprises providing a set of patterned features on the substrate, exposing the set of patterned features to a dose of ions incident on the substrate over multiple angles, and selectively etching exposed portions of the patterned features.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Inventors: Ludovic Godet, Christopher R. Hatem, Patrick M. Martin, Timothy J. Miller
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Publication number: 20120258583Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.Type: ApplicationFiled: April 5, 2012Publication date: October 11, 2012Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic GODET, Morgan D. Evans, Christopher R. Hatem
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Publication number: 20120145918Abstract: A plasma is formed from one or more gases in a plasma chamber using at least a first power and a second power. A first ion species is generated at said first power and a second ion species is generated at said second power. In one embodiment, the first ion species and second ion species are implanted into a workpiece at two different energies using at least a first bias voltage and a second bias voltage. This may enable implantation to two different depths. These on species may be atomic ions or molecular ions. The molecular ions may be larger than the gases used to form the plasma.Type: ApplicationFiled: December 10, 2010Publication date: June 14, 2012Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Svetlana RADOVANOV, Ludovic GODET, Christopher R. HATEM
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Patent number: 8124506Abstract: A method of using helium to create ultra shallow junctions is disclosed. A pre-implantation amorphization using helium has significant advantages. For example, it has been shown that dopants will penetrate the substrate only to the amorphous-crystalline interface, and no further. Therefore, by properly determining the implant energy of helium, it is possible to exactly determine the junction depth. Increased doses of dopant simply reduce the substrate resistance with no effect on junction depth. Furthermore, the lateral straggle of helium is related to the implant energy and the dose rate of the helium PAI, therefore lateral diffusion can also be determined based on the implant energy and dose rate of the helium PAI. Thus, dopant may be precisely implanted beneath a sidewall spacer, or other obstruction.Type: GrantFiled: July 31, 2009Date of Patent: February 28, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Ludovic Godet
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Patent number: 8101528Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.Type: GrantFiled: August 4, 2010Date of Patent: January 24, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Benjamin Colombeau
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Publication number: 20110300696Abstract: Embodiments of this doping method may be used to improve junction formation. An implant species, such as helium or another noble gas, is implanted into a workpiece to a first depth. A dopant is deposited on a surface of the workpiece. During an anneal, the dopant diffuses to the first depth. The noble gas ions may at least partially amorphize the workpiece during the implant. The workpiece may be planar or non-planar. The implant and deposition may occur in a system without breaking vacuum.Type: ApplicationFiled: June 2, 2010Publication date: December 8, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. HATEM, Ludovic GODET
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Publication number: 20110253902Abstract: An apparatus that generates molecular ions and methods to generate molecular ions are disclosed. At least a first species is ionized in an ion source. The first species ions and/or first species combine to form molecular ions. These molecular ions may be transported to a second chamber, which may be an arc chamber or diffusion chamber, and are extracted. The molecular ions may have a larger atomic mass than the first species or first species ions. A second species also may be ionized with the first species to form molecular ions. In one instance, the first and second species are both molecules.Type: ApplicationFiled: April 20, 2010Publication date: October 20, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Ludovic Godet, Svetlana Radovanov, Christopher R. Hatem
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Patent number: 8012843Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.Type: GrantFiled: August 5, 2010Date of Patent: September 6, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
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Patent number: 8003957Abstract: To implant a carbon-containing species, a gas containing carbon is ionized in the ion chamber. The ionization of this gas will typically produce a number of ionized species. However, many of these resulting ionized species are not beneficial to the desired implant, as they contain only non-carbon atoms. These species must be eliminated before the implantation, leaving only carbon-based species. However, the current of the desired species may be low, thereby requiring extra energy or time to implant the desired dosage of carbon into a substrate. This can be improved through the use of a second gas. This second gas is used to dilute the primary carbon-containing gas to be ionized in the ion chamber. By incorporating this dilution gas, more of the resulting ionized species are beneficial to the carbon implantation.Type: GrantFiled: February 9, 2009Date of Patent: August 23, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Craig R. Chaney, Adolph R. Dori, Christopher R. Hatem, Alexander S. Perel
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Publication number: 20110104618Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.Type: ApplicationFiled: November 1, 2010Publication date: May 5, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Nicholas P.T. Bateman, Helen L. Maynard, Benjamin B. Riordon, Christopher R. Hatem, Deepak Ramappa
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Publication number: 20110034014Abstract: A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Jay T. Scheuer
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Publication number: 20110033998Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.Type: ApplicationFiled: August 5, 2010Publication date: February 10, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
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Publication number: 20110034013Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Benjamin Colombeau
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Formation Of Raised Source/Drain On A Strained Thin Film Implanted With Cold And/Or Molecular Carbon
Publication number: 20100279479Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions.Type: ApplicationFiled: May 1, 2009Publication date: November 4, 2010Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Helen L. Maynard, Deepak A. Ramappa