Abstract: A wiper apparatus for a window includes a wiper arm having an injection molded body with a chamber formed therein. The chamber is formed with a gas and the chamber selectively directs a fluid to a nozzle.

Abstract: A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

Abstract: A cup holder, wherein the cup holder comprises a well adapted to receive a beverage container through an open top of the well. The cup holder also includes a sealing unit having a ring seal secured to the well adjacent to the open top of the well. The ring seal engages the container when the container is disposed in the well to cooperate with the well in providing a substantially closed and sealed chamber resistant to heat transfer to or from the chamber.

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: A vehicle bumper is disclosed that includes a first vehicle mounting member, a second vehicle mounting member and an elongated energy absorbing structure. The first and second vehicle mounting members are configured to be attached to a vehicle at horizontally spaced apart locations and to support the vehicle bumper. The elongated energy absorbing structure is movably attached to both of the vehicle mounting members to linearly deform and torsionally deform with respect to the mounting members in response to a vehicular impact. The vehicle bumper absorbs energy linearly and torsionally in response to vehicular impact.

Abstract: An NDE test data record management system is provided. The test data record management system can include a format conversion server, a local archiving server, a cataloging server, an image and data cache server, and an image query and review station.

Abstract: A system and method are disclosed for securely handling data and information that may be used by an electronic information system. This includes storing and accessing data on a medium that has the appearance of a standard CD or DVD, but is novel in comparison thereto as to its structure and content. The system and method may be embodied in media that have characteristics of a CD or DVD but can take any shape permitted for a CD or DVD. Further, the system and method may be used for interconnection of electronic devices without the need of cables or conventional wireless connections. And, the system and method may provide for secure storage of data or information downloaded from a source, such music from the Internet.

Abstract: A processor of an apparatus in one example makes a determination of an environmental characteristic based on an average of a plurality of concomitant values that correspond to the environmental characteristic.

Abstract: A processor of an apparatus in one example makes a determination of an environmental characteristic based on a plurality of concomitant values that correspond to the environmental characteristic. A plurality of sensors obtains the plurality of concomitant values. The plurality of sensors configured in a plurality of orientations.

Abstract: A vehicle bumper is disclosed that includes a first vehicle mounting member, a second vehicle mounting member and an elongated energy absorbing structure. The first and second vehicle mounting members are configured to be attached to a vehicle at horizontally spaced apart locations and to support the vehicle bumper. The elongated energy absorbing structure is movably attached to both of the vehicle mounting members to linearly deform and torsionally deform with respect to the mounting members in response to a vehicular impact. The vehicle bumper absorbs energy linearly and torsionally in response to vehicular impact.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: A method for protecting a dynamically reconfigurable computing system includes generating an encoding signature and passing the encoding signature, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library contains a plurality of functions for selective programming into the at least one field programmable logic device. A lock is generated so as to prevent external resources with respect to the system from accessing the encoding signature during the passing thereof.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: Methods and systems are provided for web site construction, including method and system for using page modules for facilitating web site construction without requiring the user to have specialized knowledge of web site coding techniques.

Abstract: A system and method are disclosed that may used to significantly reduce the costs of printing documents. This will involve the use of remanufactured printer cartridges and printing only changed pages after the first printing of a particular document. The system and method also will permit an accurate determination of printing costs based on the incremental price of the paper and the cost the ink/toner necessary for printing each page of a document. The system and method may be carried out in a computer-based system with a connected printer, and the computer-based system connects to a central system.

Abstract: A field programmable gate array is described for use in a semiconductor chip such as a VLSI chip. The array is provided with variable wire-through porosity to allow for optimum chip-level routing through the array. This is achieved by dividing the array into blocks which can be individually assessed for required porosity. Then blocks that have been prefabricated with differing porosities are placed in the macro to optimize local chip level routing. The routing of wires is determined by developing a chip floor plan to include early timing allocation and a proposed placement of the array. The floor plan is then overlaid with critical logical wiring nets. From this, an initial selection of blocks is made based on proposed wiring density, and the macro is assembled with the blocks strategically placed therein. The procedure is likewise applicable to other types of densely obstructed cores embedded with a chip.

Abstract: A method and system for modifying the function of a state machine having a programmable logic device. The method including: (a) modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; (b) generating a programmable logic device netlist from differences in the high-level design and the modified design; and (c) installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.