Abstract: Methods and apparatuses for transferring heat from microelectronic device modules are disclosed. An apparatus in accordance with one embodiment of the invention can include first and second heat transfer portions positioned to face toward opposing faces of a microelectronic device module. Heat transfer fins having different length can extend away from at least one of the heat transfer portions. In one embodiment, the heat transfer fins can be integrally formed with other portions of the apparatus. In other embodiments, modules carrying the heat transfer devices can be mounted at an acute angle relative to a support structure (such as a PCB) so that heat transfer fins from one module can extend adjacent to the end region of the neighboring module. This arrangement can increase the rate at which heat is transferred away from the modules, and can increase the utilization of a limited heat transfer volume within a device, such as a computer.

Abstract: A method and apparatus for controlling multiple signal polarity in a memory device. A desired active state signal polarity of at least one signal pad of a device is compared to a default active state signal polarity allocated to the at least one signal pad. The desired and default active state signal polarities have either a high active state or a low active state. The active state signal polarity of the at least one signal pad is reversed in response to the desired active state signal polarity differing from the default active signal polarity.

Abstract: A positive electrode for an electrochemical cell including a lithium transition-metal-oxide or lithium-transition metal-oxyfluoride having deposited thereon at least one oxide, oxyhydroxide or hydroxide of zirconium, aluminum, titanium, yttrium, silicon or mixtures thereof, the particles being less than 25 nm in longest dimension, but preferably less than 4 nm. A complete cell as well as a battery incorporating the positive electrode is disclosed as is a method of making the positive electrode, cell and battery.

Abstract: A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

Abstract: A memory module includes a memory device, a connector, a plurality of lines coupling the memory device and the connector, and termination circuitry coupled to at least a subset of the lines. A method for terminating a memory bus includes providing at least two expansion sockets coupled to the memory bus; interfacing two expansion memory modules including termination circuitry with the expansion sockets; and disabling the termination circuitry for one of the expansion memory modules.

Abstract: A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

Abstract: A method of operating an electrochemical cell is disclosed. The cell has an intermetallic negative electrode of Cu6-xMxSn5, wherein x is ≦3 and M is one or more metals including Si and a positive electrode containing Li in which Li is shuttled between the positive electrode and the negative electrode during charge and discharge to form a lithiated intermetallic negative electrode during charge. The voltage of the electrochemical cell is controlled during the charge portion of the charge-discharge cycles so that the potential of the lithiated intermetallic negative electrode in the fully charged electrochemical cell is less than 0.2 V but greater than 0 V versus metallic lithium.

Abstract: A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO2.(1−x)Li2M′O3 in which 0<x<1, and where M is more than one ion with an average trivalent oxidation state and with at least one ion being Ni, and where M′ is one or more ions with an average tetravalent oxidation state. Complete cells or batteries are disclosed with anode, cathode and electrolyte as are batteries of several cells connected in parallel or series or both.

Abstract: A golf card game which utilizes one or more decks of playing cards with each deck being divided into four different suits and there being fourteen different numerical value of cards within each suit. Each deck of playing cards also includes a prescribed number of wild cards. There being separate from the playing cards golf hole representations with each representation to display a golf hole number, a par value for the golf hole number, wild card numbers and a numerical value determining a number of the playing cards that are to be dealt to each player when playing a golf hole number. There is also to be used a plurality of stroke card representations which are numerically sequentially arranged which start with the number 1 and proceed to at least number 5. Cards are to be then dealt to all players and melds to be produced by a player, and when a player has completely melded and the first player to produce all melds will be declared the winner of a given hand and assigned a numerical score.

Abstract: A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

Abstract: A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO2.(1−x)Li2M′O3 in which 0<x<1, and where M is one or more ion with an average trivalent oxidation state and with at least one ion being Mn or Ni, and where M′ is one or more ion with an average tetravalent oxidation state. Complete cells or batteries are disclosed with anode, cathode and electrolyte as are batteries of several cells connected in parallel or series or both.

Abstract: One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.

Abstract: A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO2.(1-x)Li2M′O3 in which 0<x<1, and where M is one or more trivalent ion with at least one ion being Mn or Ni, and where M′ is one or more tetravalent ion. Complete cells or batteries are disclosed with anode, cathode and electrolyte as are batteries of several cells connected in parallel or series or both.

Abstract: A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by programming a portion of a mode register of the memory device or by setting one or more programmable elements. For read operations, the synchronous memory device internally reads data corresponding to the largest supported prefetch size, and outputs read data corresponding to the current mode. For write operations the synchronous memory accepts write data corresponding to the selected prefetch mode and writes the received data to the array. Data words corresponding to data not received are masked from writing via a write masking circuit.

Abstract: Lithium metal oxide compounds of nominal formula Li2MO2, in which M represents two or more positively charged metal ions, selected predominantly and preferably from the first row of transition metals are disclosed herein. The Li2MO2 compounds have a layered-type structure, which can be used as positive electrodes for lithium electrochemical cells, or as a precursor for the in-situ electrochemical fabrication of LiMO2 electrodes. The Li2MO2 compounds of the invention may have additional functions in lithium cells, for example, as end-of-discharge indicators, or as negative electrodes for lithium cells.

Abstract: A positive electrode for a non-aqueous lithium cell or battery in which the positive electrode comprising a LiMn2−xMxO4 spinel structure in which M is one or more cations with an atomic number less than 52, such that the average oxidation state of the manganese ions is equal to or greater than 3.5, and in which 0≦x≦0.15, having one or more lithium spine oxide LiM′2O4 or lithiated spinel oxide Li1+yM′2O4 compounds in which the M′ cations are selected from one or more of lithium, cobalt, titanium or manganese and in which 0<y≦1.

Abstract: A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.

Abstract: A memory module includes a memory device, a connector, a plurality of lines coupling the memory device and the connector, and termination circuitry coupled to at least a subset of the lines. A method for terminating a memory bus includes providing at least two expansion sockets coupled to the memory bus; interfacing two expansion memory modules including termination circuitry with the expansion sockets; and disabling the termination circuitry for one of the expansion memory modules.