Abstract: Traffic management reports are created from data provided by vehicle sensor devices placed at different fixed locations in a region. Data of vehicles that pass each of the vehicle sensor devices are captured and communicated to a central computer database. At the central computer database, traffic management reports are periodically created from the vehicle data. Each traffic management report incorporates vehicle data from a plurality of vehicles. The vehicle data is for a plurality of previous, non-current times so as to allow for analysis of past vehicle data.

Abstract: New methods and systems are disclosed for improved assessments of student progress in education. Using a new concept called a cumulative test, examinee ability may be measured by combining discrete measures into one test representing ability measured over an extended period of time. (FIG. 1.) Many assessment items and corresponding responses from various different test forms may contribute to a cumulative test. The discrete or “snapshot” tests taken into account preferably are given over an extended period such as a school year, in different classes, schools and even districts. (FIG. 2.) There is no requirement that examinees take the same items or any particular set of items to implement the cumulative test. Item Response Theory (IRT) may be used to estimate ability scores for cumulative tests (FIG. 3.).

Abstract: The disclosed embodiments provide a battery cell. The battery cell includes an anode containing an anode current collector and an anode active material disposed over the anode current collector. The battery cell also includes a cathode containing a cathode current collector and a cathode active material disposed over the cathode current collector. The cathode active material has a composition represented by xLi2MO3.(1-x)LiCoyM?(1-y)O2.

Abstract: The present invention provides an electrode material suitable for use as a cathode in a sodium electrochemical cell or battery, the electrode comprising a layered material of formula NacLidNieMnfMzOb, wherein M comprises one or more metal cation, 0.24?c/b?0.5, 0<d/b?0.23, 0?e/b?0.45, 0?f/b?0.45, 0?z/b?0.45, the combined average oxidation state of the metal components (i.e., NacLidNieMnfMz) is in the range of about 3.9 to 5.2, and b is equal to (c+d+Ve+Xf+Yz)/2, wherein V is the average oxidation state of the Ni, X is the average oxidation state of the Mn, and Y is the average oxidation state of the M in the material. The combined positive charge of the metallic elements is balanced by the combined negative charge of the oxygen anions, the Na is predominately present in a sodium layer, and the Mn, Ni, and M are predominately present in a transition metal layer.

Abstract: This invention provides lithium-rich compounds as precursors for positive electrodes for lithium cells and batteries. The precursors comprise a Li2O-containing compound as one component, and a second charged or partially-charged component, selected preferably from a metal oxide, a lithium-metal-oxide, a metal phosphate or metal sulfate compound. Li2O is extracted from the above-mentioned electrode precursors to activate the electrode either by electrochemical methods or by chemical methods. The invention also extends to methods for synthesizing and activating the precursor electrodes and to cells and batteries containing such electrodes.

Abstract: The present invention provides a nanostructured metal oxide material for use as a component of an electrode in a lithium-ion or sodium-ion battery. The material comprises a nanostructured titanium oxide or vanadium oxide film on a metal foil substrate, produced by depositing or forming a nanostructured titanium dioxide or vanadium oxide material on the substrate, and then charging and discharging the material in an electrochemical cell from a high voltage in the range of about 2.8 to 3.8 V, to a low voltage in the range of about 0.8 to 1.4 V over a period of about 1/30 of an hour or less. Lithium-ion and sodium-ion electrochemical cells comprising electrodes formed from the nanostructured metal oxide materials, as well as batteries formed from the cells, also are provided.

Abstract: Traffic management reports are created from data provided by vehicle sensor devices placed at different fixed locations in a region. Data of vehicles that pass each of the vehicle sensor devices are captured and communicated to a central computer database. At the central computer database, traffic management reports are periodically created from the vehicle data. Each traffic management report incorporates vehicle data from a plurality of vehicles. The vehicle data is for a plurality of previous, non-current times so as to allow for analysis of past vehicle data.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: Traffic management reports are created by providing vehicle sensor devices at different location in a region. Each device captures data of vehicles that pass the device. The vehicle data is communicated to a central computer database. At the central computer database, a user interface selects one or more criteria from a plurality of criteria for filtering the vehicle data. Traffic management reports are then automatically created from the filtered vehicle data using the selected criteria.

Abstract: A method of stabilizing a metal oxide or lithium-metal-oxide electrode comprises contacting a surface of the electrode, prior to cell assembly, with an aqueous or a non-aqueous acid solution having a pH greater than 4 but less than 7 and containing a stabilizing salt, for a time and at a temperature sufficient to etch the surface of the electrode and introduce stabilizing anions and cations from the salt into said surface. The structure of the bulk of the electrode remains unchanged during the acid treatment. The stabilizing salt comprises fluoride and at least one cationic material selected from the group consisting of ammonium, phosphorus, titanium, silicon, zirconium, aluminum, and boron.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: This invention provides a lithium-oxygen or lithium-air electrochemical cell comprising a negative electrode, an electrolyte, and a porous activated positive electrode comprising lithium-rich electrocatalytic materials suitable for use in lithium-oxygen (air) cells and batteries. The activated positive electrode is produced by activating a precursor electrode formed from a material comprising one or more metal oxide compounds of general formula xLi2O.yMOz, in which 0<x?4, 0<y?1, and 0<z?3, in which M is typically, but not exclusively, a transition metal, excluding Li2MnO3 as a sole metal oxide compound in the precursor electrode. Li2O is extracted from the above-mentioned precursors to activate the electrode either by electrochemical methods or by chemical methods. The invention extends to batteries containing such electrochemical cells.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.

Abstract: A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.

Abstract: The present invention provides an electrode material suitable for use as a cathode in a sodium electrochemical cell or battery, the electrode comprising a layered material of formula NacLidNieMnfMzOb, wherein M comprises one or more metal cation, 0.24?c/b?0.5, 0<d/b?0.23, 0?e/b?0.45, 0?f/b?0.45, 0?z/b?0.45, the combined average oxidation state of the metal components (i.e., NacLidNieMnfMz) is in the range of about 3.9 to 5.2, and b is equal to (c+d+Ve+Xf+Yz)/2, wherein V is the average oxidation state of the Ni, X is the average oxidation state of the Mn, and Y is the average oxidation state of the M in the material. The combined positive charge of the metallic elements is balanced by the combined negative charge of the oxygen anions, the Na is predominately present in a sodium layer, and the Mn, Ni, and M are predominately present in a transition metal layer.