Patents by Inventor Christopher S. MacLellan

Christopher S. MacLellan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8270322
    Abstract: A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: September 18, 2012
    Assignee: EMC Corporation
    Inventors: Almir Davis, Jeffrey S. Kinne, Christopher S. MacLellan, Stephen L. Scaringella
  • Patent number: 7987229
    Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 26, 2011
    Assignee: EMC Corporation
    Inventors: Jeffrey Kinne, John O'Shea, Michael Sgrosso, William F. Baxter, III, Christopher S. MacLellan
  • Patent number: 7712004
    Abstract: An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 4, 2010
    Assignee: EMC Corporation
    Inventors: Brian K. Campbell, Kendell A. Chilton, Christopher S. MacLellan, Ofer Porat
  • Patent number: 7707367
    Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: April 27, 2010
    Assignee: EMC Corporation
    Inventors: Nhut Tran, Michael Sgrosso, William F. Baxter, III, Christopher S. MacLellan
  • Patent number: 7631128
    Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: December 8, 2009
    Assignee: EMC Corporation
    Inventors: Michael Sgrosso, William F. Baxter, III, Jeffrey Kinne, Christopher S. MacLellan, John O'Shea
  • Patent number: 7401271
    Abstract: A testing system (and method of using same) for testing a system-under-test (SUT) are provided. One embodiment of the testing system includes first, second, and third logic sections. The third logic section selectively couples either the first logic section or the second logic section to the SUT, based upon two control signals transmitted to the third logic section. One of the control signals is transmitted from a source external to the SUT, first logic section, second logic section, and third logic section. The other control signal is transmitted from the first logic section. When the third logic section couples the first logic section to the SUT, the first logic section may transmit one or more test-related signals to the SUT. When the third logic section couples the second logic section to the SUT, the second logic section may transmit one or more other signals to the SUT.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: July 15, 2008
    Assignee: EMC Corporation
    Inventor: Christopher S. MacLellan
  • Patent number: 7400672
    Abstract: A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 15, 2008
    Assignee: EMC Corporation
    Inventors: Almir Davis, Jeffrey S. Kinne, Christopher S. MacLellan, Stephen L. Scaringella
  • Patent number: 7337250
    Abstract: A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 26, 2008
    Assignee: EMC Corporation
    Inventors: Almir Davis, Jeffrey S. Kinne, Christopher S. MacLellan, Stephen L. Scaringella
  • Patent number: 7272668
    Abstract: A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: September 18, 2007
    Assignee: EMC Corporation
    Inventors: John K. Walton, Ofer Porat, Christopher S. MacLellan, Daniel Castel, Kendell A. Chilton, Brian K. Campbell, Gregory S. Robidoux, Brian D. Magnuson
  • Patent number: 7254654
    Abstract: A data transfer device is disclosed for writing data to and reading data from a disk drive system through a plurality of ports of the data transfer device. The data transfer device includes a first buffer for serially receiving, from a host system, control portions of data read requests and data write transfers; a second buffer for serially receiving, from the host system, data portions of data write transfers received by the first buffer; and N temporary storage devices, wherein N is a positive integer, coupled to the first buffer and the second buffer, the N temporary storage devices for parallelly receiving and temporarily storing consecutive control portions of the data read transfers and data write transfers from the first buffer. Up to N of the data read transfers and data write transfers are transferred to the disk drive system through the plurality of ports simultaneously.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: August 7, 2007
    Assignee: EMC Corporation
    Inventors: Almir Davis, Christopher S. MacLellan
  • Patent number: 7149947
    Abstract: A data processing system includes an input portion for receiving a digital word having N bits of data and M bits for error detection, a first error correction code generator for generating a first error correction code based on the N bits of data of the digital word and a second error correction code generator for generating a second error correction code based on the N bits of data of the digital word. A first logic operator performs a first logic operation on the first error correction code and the second error correction code to generate a data signature representative of a comparison of the first error correction code and the second error correction code and a second logic operator performs a second logic operation on the data signature and the M bits of the digital word to generate a constant signal representing a comparison of the data signature and the M bits of the digital word.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: December 12, 2006
    Assignee: EMC Corporation
    Inventors: Christopher S. MacLellan, Paul G. Scharlach
  • Patent number: 7073031
    Abstract: A system for maintaining data coherency. The system includes a plurality of processors. A plurality of resources is also included. One portion of the resources is sharable with the plurality of processors and each one of the other ones of the resources being dedicated to a predetermined one of the processors. The system also includes a plurality of buffers. Each one of the buffers is associated with a corresponding one of the plurality of processors. Each one of the buffers is adapted to successively store information presented thereto in successive locations of such one of the buffers. The information includes requests from the corresponding one of the processor. The system includes a logic section responsive to each one of the requests provided by the plurality of processors. The logic section produces indicia indicating whether or not such one of the requests is a request for an operation with one of the sharable resources.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 4, 2006
    Assignee: EMC Corporation
    Inventors: Christopher S. MacLellan, Avinash Kallat, Almir Davis, Stephen L. Scaringella
  • Patent number: 7007194
    Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: February 28, 2006
    Assignee: EMC Corporation
    Inventors: Paul C. Wilson, Mark Zani, Farouk Khan, Christopher S. MacLellan, John K. Walton, Steven MacArthur, Kendall A. Chilton, William Tuccio, Robert A. Thibault
  • Patent number: 6993705
    Abstract: A method for determining Cyclic Redundancy Check (CRC) parity of data, such data comprising a plurality of bytes, each one of the bytes having a parity bit, the plurality of bytes of data having a CRC. The method includes generating the parity of the parity bits of the plurality of bytes of the data, such generated parity being the parity of the CRC of such data. The method includes: generating parity of the parity bits of the plurality of data bytes; and comparing such generated parity with the parity bit of the CRC of the data. The method receives data having a plurality of N bytes: [D(0), D(1), . . . , D(N?1]) each byte having a parity bit p and computes the parity of [P(0), P(1), . . . P(N?1)].
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: January 31, 2006
    Assignee: EMC Corporation
    Inventor: Christopher S. MacLellan
  • Patent number: 6910145
    Abstract: In one embodiment of the present invention, a system is provided for use in transmitting data and related control information from a first clock domain to a second clock domain. The system may include a first logic section that may generate respective identification information that may be used to identify respective types of information represented by respective data and related control information. The system may also include memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and related control information. The memory also may store, in association with the respective data and related control information, the respective identification information. The memory may be configured to permit the retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: June 21, 2005
    Assignee: EMC Corporation
    Inventors: Christopher S. MacLellan, Gregory S. Robidoux, John K. Walton, Kendell A. Chilton
  • Patent number: 6904556
    Abstract: A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: June 7, 2005
    Assignee: EMC Corporation
    Inventors: John K. Walton, Michael Bermingham, Christopher S. MacLellan
  • Patent number: 6886116
    Abstract: A system for validating error detection logic in a system. The system includes a plurality of information paths, each one of such paths having associated therewith an error detection logic, each one of the paths having a plurality of information bits. A test word buffer is provided for receiving a test word, such test word indicating a particular one of the plurality of information bits in a particular one of the information paths to be corrupted. The system includes a plurality of fault injectors responsive to the test word received by the buffer. Each one of the fault injectors is disposed in a corresponding one of the information paths prior to the associated the error detection logic. Each one of such fault injectors corrupts a selected one of the information bits in the corresponding one of the information paths in response to the test word received by the buffer to test whether the associated error detection logic detects such injected fault.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: April 26, 2005
    Assignee: EMC Corporation
    Inventors: Christopher S. MacLellan, John K. Walton
  • Patent number: 6882620
    Abstract: According to one embodiment, a system for controlling passing of a token among a plurality of clients that access a shared resource includes at least one controller. The at least one controller is configured to cause the token to be passed to each of the plurality of clients when the system is in a first state, and to cause the token to be passed to fewer than all of the plurality of clients when the system is in a second state. According to another embodiment, a token-ring system includes a shared resource, at least first and second clients that access the shared resource, and error detection logic. The first client includes a primary device and a secondary device which provides bootstrap information to the primary device. The error detection is configured to directly monitor the secondary device for an anomaly in the operation thereof. According to yet another embodiment, a method is disclosed for operating a multi-port memory including at least first and second memory ports that access a shared memory.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: April 19, 2005
    Assignee: EMC Corporation
    Inventors: Christopher S. MacLellan, John K. Walton
  • Patent number: 6883072
    Abstract: A memory system and method of using same are provided. In one embodiment of the present invention, the memory system may include a plurality of logic sections that may be used to facilitate execution of relatively complex atomic read-modify-write operations.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: April 19, 2005
    Assignee: EMC Corporation
    Inventors: John K. Walton, Christopher S. MacLellan
  • Patent number: 6877061
    Abstract: A method and system for producing a data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface has a plurality of first directors, a plurality of second directors, and a global memory. The method includes: providing a backplane having slots adapted to have plugged therein a plurality of printed circuit board. The printed circuit boards include: a plurality of first director boards having the first directors; a plurality of second printed circuit boards having the second directors; a plurality of memory printed circuit boards providing the global memory; a plurality of dummy first director boards having first jumpers; a plurality of dummy second director boards having second jumpers; a plurality of dummy memory boards having third jumpers.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: April 5, 2005
    Assignee: EMC Corporation
    Inventors: Robert A. Thibault, Daniel Castel, Brian Gallagher, Paul C. Wilson, John K. Walton, Christopher S. MacLellan