Abstract: Techniques are disclosed for managing artificial intelligence model partitions for execution in an information processing system with edge computing resources. For example, a method comprises the following steps. An intermediate representation of an artificial intelligence model is obtained. A computation graph is generated based on the intermediate representation. The computation graph is partitioned into a set of partitions. The method then schedules the set of partitions for respective execution on a set of computing devices in an edge computing environment, and causes deployment of the set of partitions respectively to the set of computing devices for execution in the edge computing environment.

Abstract: Techniques are disclosed for scheduling artificial intelligence model partitions for execution in an information processing system. For example, a method comprises the following steps. An intermediate representation of an artificial intelligence model is obtained. A reversed computation graph corresponding to a computation graph generated based on the intermediate representation is obtained. Nodes in the reversed computation graph represent functions related to the artificial intelligence model, and one or more directed edges in the reversed computation graph represent one or more dependencies between the functions. The reversed computation graph is partitioned into sequential partitions, such that the partitions are executed sequentially and functions corresponding to nodes in each partition are executed in parallel.

Abstract: Techniques described herein relate to a method for deploying workflows. The method may include obtaining, by a registration manager associated with accelerator pools, a first request from a client to perform a portion of a first workflow using accelerators; identifying a minimum quantity and a maximum quantity of accelerators associated with the first request; identifying an accelerator pool of the accelerator pools to perform the portion of the first workflow based on the minimum quantity and the maximum quantity of accelerators, where the accelerator pool includes at least the maximum quantity of accelerators; establishing a connection between the client and the accelerators of the accelerator pool to perform the portion of the first workflow; and initiating performance of the portion of the first workflow, wherein the portion of the first workflow is performed using at least the minimum quantity of accelerators.

Abstract: Techniques described herein relate to a method for managing workflows. The method may include obtaining, from a client, by a registration manager associated with accelerator pools, a request to perform a portion of a workflow using accelerators; identifying a minimum quantity and a maximum quantity of accelerators associated with the request; identifying a storage to store data associated with the portion of the workflow; identifying an accelerator pool of the accelerator pools that includes at least the maximum quantity of accelerators; establishing a connection between the client, the storage, and accelerators of the accelerator pool to perform the portion of the workflow; and initiating the performance of the portion of the workflow using the storage, the client, and the accelerators of the accelerator pool.

Abstract: Techniques for model parameter sharing between inference model instances are disclosed. For example, a method performed by a first process obtains a representation of an inference model for which multiple instances of the inference model are to be executed on at least one processing unit. The method determines, from the representation of the inference model, one or more model parameters that are a pre-trained type of model parameter. The method allocates a shared memory for storing the one or more model parameters that are the pre-trained type of model parameter. The method stores the one or more model parameters that are the pre-trained type of model parameter in the shared memory for access by the multiple instances of the inference model to be executed on the at least one processing unit.

Abstract: One example method includes transmitting, by an application running in a host CPU, a notification to an application in a coprocessor/accelerator indicating that inbound data generated by the application is ready, receiving, by the application in the coprocessor/accelerator, the notification and delegating, by the application in the coprocessor/accelerator, an IO command to the application running in the host CPU, forwarding, by the application running in the host CPU, the IO command to an OS of the host CPU, transmitting, by the OS of the host CPU, an IO request to an IO device, initiating, by the IO device, a P2PDMA to transmit data associated with the IO request to a memory of the coprocessor/accelerator, and processing, by the application in the coprocessor/accelerator, the data.

Abstract: In an information processing system with at least a first node and a second node separated from the first node, and each of the first node and the second node configured to execute an application in accordance with at least one entity that moves from a proximity of the first node to a proximity of the second node, a method maintains, as part of a context at the first node, a set of status indicators for a set of computations associated with a computation graph representing at least a portion of the execution of the application at the first node. Further, the method causes the transfer of the context from the first node to the second node to enable the second node to continue execution of the application using the transferred context from the first node.

Abstract: A decoupled artificial intelligence model management architecture comprises a front-end component, a scheduler component and a back-end component configured to enable an open and dynamic system which accepts any models from any formats to be deployed on any target devices and to dynamically change scheduling of parallelism, parameter movements and computation executions across the target devices.

Abstract: Techniques are disclosed for managing artificial intelligence model partitions for execution in an information processing system with edge computing resources. For example, a method comprises the following steps. An intermediate representation of an artificial intelligence model is obtained. A computation graph is generated based on the intermediate representation. The computation graph is partitioned into a set of partitions. The method then schedules the set of partitions for respective execution on a set of computing devices in an edge computing environment, and causes deployment of the set of partitions respectively to the set of computing devices for execution in the edge computing environment.

Abstract: Techniques are disclosed for scheduling artificial intelligence model partitions for execution in an information processing system. For example, a method comprises the following steps. An intermediate representation of an artificial intelligence model is obtained. A reversed computation graph corresponding to a computation graph generated based on the intermediate representation is obtained. Nodes in the reversed computation graph represent functions related to the artificial intelligence model, and one or more directed edges in the reversed computation graph represent one or more dependencies between the functions. The reversed computation graph is partitioned into sequential partitions, such that the partitions are executed sequentially and functions corresponding to nodes in each partition are executed in parallel.

Abstract: One example method includes transmitting, by an application running in a host CPU, a notification to an application in a coprocessor/accelerator indicating that inbound data generated by the application is ready, receiving, by the application in the coprocessor/accelerator, the notification and delegating, by the application in the coprocessor/accelerator, an IO command to the application running in the host CPU, forwarding, by the application running in the host CPU, the IO command to an OS of the host CPU, transmitting, by the OS of the host CPU, an IO request to an IO device, initiating, by the IO device, a P2PDMA to transmit data associated with the IO request to a memory of the coprocessor/accelerator, and processing, by the application in the coprocessor/accelerator, the data.

Abstract: One example method includes transmitting, by an application running in a host CPU, a notification to an application in a coprocessor/accelerator indicating that inbound data generated by the application is ready, receiving, by the application in the coprocessor/accelerator, the notification and delegating, by the application in the coprocessor/accelerator, an IO command to the application running in the host CPU, forwarding, by the application running in the host CPU, the IO command to an OS of the host CPU, transmitting, by the OS of the host CPU, an IO request to an IO device, initiating, by the IO device, a P2PDMA to transmit data associated with the IO request to a memory of the coprocessor/accelerator, and processing, by the application in the coprocessor/accelerator, the data.

Abstract: A system for arbitrating a transmission of data includes a number K of transmitters, a request signal transmission device, a device valid signal transmission device, and a data valid logic device, wherein a transmitter asserts a request signal to request permission to begin a data transmission and transmits transmission-identifying information to a receiver. The data valid logic device deasserts a data valid signal based on the state of a wait signal, thereby preventing a transmission of data from each of the K transmitters at one clock cycle after a clock cycle at which the data signal is deasserted. An arbitration logic device of the receiver selects one of the number K of transmitters to grant permission to transmit data to the receiver and outputs an arbitration signal to a wait logic device instructing the wait logic device to deassert the wait signal of the selected trnasmitter.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: An error checking system includes an input device for receiving a data element including parity information; a parity check device for checking the parity information of the data element to determine whether the data element is valid; a CRC generator coupled to the parity check device for generating a CRC for the data element; and an output device for transmitting the data element with the parity information and CRC to a downstream device over a transmission link. The parity check device is operative to output a corruption signal to the CRC generator if the parity check device determines that the data element is invalid, to instruct the CRC generator to corrupt the CRC generation for that data element.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A testing system (and method of using same) for testing a system-under-test (SUT) are provided. One embodiment of the testing system includes first, second, and third logic sections. The third logic section selectively couples either the first logic section or the second logic section to the SUT, based upon two control signals transmitted to the third logic section. One of the control signals is transmitted from a source external to the SUT, first logic section, second logic section, and third logic section. The other control signal is transmitted from the first logic section. When the third logic section couples the first logic section to the SUT, the first logic section may transmit one or more test-related signals to the SUT. When the third logic section couples the second logic section to the SUT, the second logic section may transmit one or more other signals to the SUT.

Abstract: A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

Abstract: A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.