Abstract: A memory system and method of using same are provided. In one embodiment of the present invention, a novel memory operation protocol may be used to facilitate the execution of memory operations in the memory system. These memory operations may include atomic read-modify-write operations that may involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the prior art.

Abstract: A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.

Abstract: A method and system for providing parity protection to data. The method and system includes transmitting pairs of groups of bits. Each one of the groups of bits has bits representing the data and a parity bit. The parity sense of one of the pair of groups of bits is opposite to the parity sense of the other one of the pair of groups of bits. The transmitted pair of groups of bits are received. The received pair of groups of bits are parity checked to determine whether the parity sense of one of the received pair of groups, of bits is opposite to the parity sense of the other one of the received pair of groups of bits. With such an arrangement, a failure in the data driver or data receiver which causes the output of all bits produced by such driver to assume the same logic state can be detected because the received pair of groups of bits will have, with such failure, the same parity sense. The method and system also includes transmitting successive groups of bits in response to clock pulses.

Abstract: A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a plurality of memory regions and a plurality of control logic sections arranged in a matrix of rows and columns. The control logic sections in each one of the rows thereof is connected to a corresponding one of the plurality of memory regions. The control logic sections in each one of the columns thereof is connected to a corresponding one of the control/data buses. Each one of the rows of control logic sections are interconnected through an arbitration bus. The control logic section is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic section.

Abstract: A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a memory and a plurality of control logic sections interconnected through an arbitration bus. Each one of the control logic sections is coupled between a corresponding one of the control/data buses and the memory. Each one of such control logic sections includes a control logic for controlling transfer of data between the memory and the one of the plurality of control/data buses coupled to said one of the logic sections. The control logic is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic. Each one of the control logic sections also includes a bus arbitration section coupled to the arbitration bus.

Abstract: A data storage system having a plurality of addressable memories for storing a global variable. Each one of a plurality of controllers is adapted to request an operation on first and second data stored in the addressable memories. Each one of the addressable memories includes: a control logic for receiving the operation request and addresses of the first and second data from one of the controllers; a random access memory; and a buffer memory coupled between the bus and a random access memory. The buffer memory has a write buffer memory adapted to store the first data in response to the control logic and a read buffer memory adapted to store the second data. The second data is read from the random access memory in response to the control logic. The buffer memory includes an operation selection section having a plurality of operation units configured to perform a different predetermined operation on the first and second data fed to a pair of input ports thereof.

Abstract: A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a plurality of memory regions and a plurality of control logic sections arranged in a matrix of rows and columns. The control logic sections in each one of the rows thereof is connected to a corresponding one of the plurality of memory regions. The control logic sections in each one of the columns thereof is connected to a corresponding one of the control/data buses. Each one of the rows of control logic sections are interconnected through an arbitration bus. The control logic section is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic section.

Abstract: A method and apparatus for hot-plugging circuit boards having lower voltage logic devices into a higher voltage backplane in a manner that minimizes overvoltage stress during system power-up, or during a lower voltage power failure. The method and apparatus ensures that the lower voltage device(s') power input reaches at least a nominal input level before any other inputs of the device are driven to a level greater than or equal to an expected input level. Dedicated output pins on lower voltage logic device(s) are configured to issue a control output signal for enabling higher voltage devices. Output enable terminals for the higher voltage parts, which are connected to respective control outputs from a lower voltage device, are normally in a disabled state as a function of pull-up or pull-down circuitry.

Abstract: An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap.

Abstract: A buffer memory includes at least one memory including a plurality of memory locations, and at least one write-control circuit. When data is written to one of the plurality of memory locations, the at least one write-control circuit causes at least one bit of validation information to be written to the at least one memory to indicate that the data written to the one of the plurality of memory locations is valid. In response to data being read from the one of the plurality of memory locations, the at least one write-control circuit causes the at least one bit of validation information to be overwritten to indicate that the data stored in the one of the plurality of memory locations is invalid.

Abstract: A modular memory array configuration uses a combinatorial decoding device (decoder), instead of straight buffering, to effect optimal delivery of control and address signals. Each port accessing memory on the array drives a single copy of address and control signals, plus bank select signals, over a shared interface to the decoder. Bank select controls the decoder which drives the address and control to only the accessed bank. Address and control signals to all banks but the accessed bank, are pulled up (inactive) with resistors on the memory array. For N banks, log2 N bank select bits are needed. The decoder device does not need to be clocked and therefore avoids problems associated with selecting between and providing asynchronous or redundant clocks for a multi-ported shared memory with ports independent of and asynchronous to one another.

Abstract: A memory system having: a plurality of memory packages for storing words, each one of the packages being adapted to store a plurality of different bits of the word; and an error detection and correction system adapted to detect an error produced in any one of the packages in storing the digital word. With such an arrangement, an error produced by a defect in one of plurality of memory packages, each adapted to store more than one bit of a digital word, may be corrected without requiring changes to other EDACs used in a system employing such memory system. The memory system has a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction. An error correction code generator is provided for converting the digital word into a second digital word having N bits of data and P redundant bits for error detection and correction. A memory is used for storing the N+P digital word. A error correction code detector corrects an error the data read from the memory.

Abstract: A storage apparatus including a memory; a first buffer into which data words are read from said memory; and a word selector receiving on a first input data words from the buffer and on a second input data words from another source, and producing on an output for storage back into the memory data words that are selected from the first and second inputs to the word selector.

Abstract: A method of pipelining an error detection algorithm on an n-bit data word stored in a memory whereby the n-bit data word is first divided into segments. Then, each of the segments of the n-bit data word is read out from memory. Upon receiving a first of the segments, a portion of the error detection algorithm is computed using the first segment to produce a first error check result. Then a next one of the segments of the data word is received, upon which a next portion of the error detection algorithm is computed using the next segment and a most recently calculated check result of a computation of a prior portion of the error detection algorithm. This produces a revised error check result. If necessary, the above-described steps are repeated until all of the segments of the data word have been processed, wherein the revised error check result computed for the last segment is an error detection syndrome for the complete data word.