Abstract: Embodiments of gas distribution modules for use with rapid thermal processing (RTP) systems and methods of use thereof are provided herein. In some embodiments, a gas distribution module for use with a RTP chamber includes: a first carrier gas line and a first liquid line fluidly coupled to a mixer, the mixer having one or more control valves configured to mix a carrier gas from the first carrier gas line and a liquid from the first liquid line in a desired ratio to form a first mixture; a vaporizer coupled to the mixer and configured to receive the first mixture in a hollow internal volume, the vaporizer having a heater configured to vaporize the first mixture; and a first gas delivery line disposed between the vaporizer and the RTP chamber to deliver the vaporized first mixture to the RTP chamber.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: Embodiments of the invention are directed to methods and apparatus for processing of a solar substrate for making a photovoltaic device. In particular, methods and apparatus for creating a negatively charged passivation layer by are provided.

Abstract: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.

Abstract: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.

Abstract: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.

Abstract: Embodiments of the invention are directed to methods and apparatus for processing of a solar substrate for making a photovoltaic device. In particular, methods and apparatus for creating a negatively charged passivation layer by are provided.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.

Abstract: A method for fabricating a gate dielectric of a field effect transistor is provided. In one embodiment, the method includes removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer, and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma. In another embodiment, the oxide layer on the gate dielectric layer is formed by forming a thermal oxide layer, i.e., depositing the oxide layer on the gate dielectric layer.

Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.

Abstract: Defects and fixed charge in a gate dielectric near the gate dielectric-substrate interface are reduced by performing a gate dielectric relaxation anneal step prior to source-drain ion implantation, in which the wafer temperature is ramped gradually to near a melting temperature of the substrate equal to a peak post-ion implantation anneal peak temperature. The ramping rates are sufficiently gradual so that the gate dielectric is held above its reflow temperature for a significant duration.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing.

Abstract: A method of forming a gate dielectric comprising silicon and oxygen is provided. The gate dielectric may also include nitrogen or another high k material. In one aspect, forming the gate dielectric includes annealing a substrate in an oxidizing atmosphere to form a silicon oxide layer, depositing a silicon nitride layer or a high k layer on the silicon oxide layer by a vapor deposition, oxidizing an upper surface of the silicon nitride layer or high k layer, and then annealing the substrate. The gate dielectric may be formed within an integrated processing system.