Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation
Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.
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As integrated circuit technology has advanced toward smaller device sizes, the industry has searched for ways of annealing ion implanted dopant impurities that minimize diffusion of the impurities. Such diffusion can distort (deepen) shallow junction implanted regions as a function of the time and temperature over which the implanted dopants are annealed. The annealing process repairs damage to the semiconductor crystal arising during ion implantation and activates the implanted semiconductor junctions by moving the implanted dopant atoms from interstitial sites to substitutional sites in the semiconductor crystal lattice. Conventional annealing methods have typically employed radiant lamps that heat the wafer to a sufficiently high temperature to achieve the desired effect. One such method holds the wafer at an elevated temperature for a relatively long (one to sixty second) period and produces a relatively large amount of implanted dopant diffusion. For smaller device sizes (e.g., 45 nm), a faster annealing process is desired, such as a spike anneal in which the wafer temperature is ramped up to an elevated temperature and then returned to its former temperature within half a second. An even faster process that can be suitable for device sizes at or below 45 nm is flash annealing, in which the wafer temperature is raised from 400° C. to 1100° C. and then returned to 400° C. within milliseconds. While flash annealing can achieve favorable results at 45 nm, it entails a higher risk of wafer breakage because of the sudden wafer temperature excursion. The need for a reliable post-implant annealing process that will work at the lowest device sizes that the industry is now contemplating (below 45 nm, e.g., 30 nm and 15 nm) has been recently met by the dynamic surface annealing (DSA) process. This process scans a powerful micron-thin line of monochromatic laser light across the wafer at a rate such that, at any instant, only a thin shallow region of the wafer is heated to near melting (e.g., 1300° C.) for an extremely short period of time (e.g., 100 μsec), this time being kept short because the entire remainder of the wafer serves as a heat sink for the heated zone. The result is little or no diffusion of the implanted dopant atoms, enabling realization of ultra-shallow implanted junction depths, and much less risk of wafer breakage. The DSA process is disclosed in U.S. Patent application publication No. US 2003/0196996, the entire disclosure of which is incorporated herein by reference.
Typically, the DSA process is carried out immediately after ion implantation of the dopant atoms in the semiconductor crystal. The DSA annealing step may be preceded by a short but lower temperature (e.g., 800° C.) annealing step using radiant lamps to repair ion implantation damage to the crystal. Typically, during the entire DSA step, an optical absorption layer such as amorphous carbon covers the wafer surface to provide uniform process results, the optical absorber layer being removed upon completion of the DSA step with a low temperature oxygen ashing.
Upon removal of the optical absorber layer, subsequent low temperature process steps that must be carried out require raising the wafer temperature above 400° C. for relatively long time frames, so that some of the implanted dopant atoms which were placed in substitutional crystalline sites return to interstitial sites, thereby deactivating a significant fraction of the dopants in the ion implanted regions (i.e., the source, drain and gate regions). These low temperature process steps include the formation of metal-silicide contacts on the top surfaces of the implanted regions, entailing deposition of a suitable metal followed by a rapid thermal process (RTP) step above 400° C. (e.g., about 450° C.) to form the metal-silicide material. Other low temperature process steps include deposition of an etch stop (Si3N4) layer and the deposition of a thick (e.g., 5000 Å) pre-metal dielectric (PMD) layer (typically SiO2) over the etch stop layer. The formation of the PMD layer can involve heating the wafer to 600° C. to 800° C. for minutes or hours.
The problems discussed above, including the dopant deactivation by subsequent low temperature processing steps, and variation in device characteristics by oxidation of the gate stack and adjacent silicon surfaces during the removal of the amorphous carbon optical absorber layer, are more critical in devices of smaller sizes (below 45 nm), and these problems must be solved in order enable fabrication of devices smaller than 45 nm.
SUMMARYA method is provided for processing a substrate having a silicon-containing semiconductor channel and an overlying silicon-containing gate electrode separated from the channel by a thin gate dielectric layer and ion implanted source and drain regions. A metal-containing layer is deposited on top surfaces of the source-drain regions and of the gate electrode. A rapid thermal process step then heats the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The remainder of the metal-containing layer is then removed. An etch stop layer is formed over the substrate so as to cover top surfaces of the source-drain regions and of the gate electrode with the etch stop layer. An optical absorber layer is deposited over the etch stop layer. A focused line beam of radiation from an array of plural lasers is scanned across the substrate along a direction transverse to the focused line beam so as to create a surface temperature near the melting point of the substrate in a surface zone illuminated by the line beam. Thereafter, the optical absorber layer is removed.
So that the manner in which the above recited embodiments of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings in the figures are all schematic and not to scale.
DETAILED DESCRIPTIONThe DSA Process:
The DSA process will first be described with reference to the drawings of
In typical operation, the gantry beams 116, 118 are set at a particular position along the fixed rails 112, 114 and the beam source 120 is moved at a uniform speed along the gantry beams 116, 118 to scan the line beam 126 perpendicularly relative to its long dimension in a direction conveniently called the fast direction. The line beam 126 is thereby scanned from one side of the wafer 122 to the other to irradiate a 1 cm swath of the wafer 122. The line beam 126 is narrow enough and the scanning speed in the fast direction fast enough that a particular area of the wafer is only momentarily exposed to the optical radiation of the line beam 126 but the intensity at the peak of the line beam is enough to heat the surface region to very high temperatures. However, the deeper portions of the wafer 122 are not significantly heated and further act as a heat sink to quickly cool the surface region. Once the fast scan has been completed, the gantry beams 116, 118 are moved along the fixed rails 112, 114 to a new position such that the line beam 126 is moved along its long dimension extending along the slow axis. The fast scanning is then performed to irradiate a neighboring swath of the wafer 122. The alternating fast and slow scanning are repeated, perhaps in a serpentine path of the beam source 120, until the entire wafer 122 has been thermally processed. One example of optics beam source 120, illustrated in
Returning to
Integrated Processes with Minimal Dopant Deactivation:
One embodiment of an integrated process, including the DSA step, that prevents or minimizes dopant deactivation is described with reference to
We have performed annealing of the implanted regions, including rapid thermal process (RTP) and DSA, prior to contact (e.g., nickel silicide) formation in the surfaces of the source-drain regions 225 and the gate 215. This approach postpones certain low temperature process steps until after the post-implant annealing (the DSA step), which can lead to dopant deactivation in the source-drain regions and extensions 225, 230 during the later low temperature process steps. Such low temperature process steps include the heating of the wafer following nickel layer deposition to form the nickel silicide contacts. Other low temperature process steps include the deposition of an etch stop layer and the deposition of the thick (5000 Å) pre-metal dielectric (PMD) layer. In one embodiment, the DSA process step is performed after at least some of these low temperature process steps in order to avoid or reduce dopant deactivation that would otherwise occur during performance of such low temperature process steps. In one embodiment of the process sequence depicted in
The process sequence illustrated in
In the foregoing embodiment, the nickel-silicide formation including the RTP step 260 is completed prior to performance of a dynamic surface annealing or dopant activation step. This prevents post-DSA deactivation of the implanted dopant atoms by the nickel silicide formation including the RTP step 260.
In a further embodiment, the etch step layer deposition step is also performed prior to the DSA step. This further embodiment is also depicted in
In the foregoing process, the low temperature process steps of contact silicide formation and etch stop deposition are performed before dynamic surface annealing, so that these low temperature process steps cannot cause dopant deactivation after dynamic surface annealing. Also, the presence of a layer (i.e., the etch stop layer 272) underneath the ACL 276 during the DSA step prevents changes in device performance that would otherwise be caused by exposure of the silicon and polycrystalline silicon surfaces to the oxygen plasma in the post-DSA ACL removal step.
The first step (block 250 of
One challenge in carrying out the processes of
Integrated Process with Prevention of Contact Silicide Melting During DSA Using Chemical Enhancement of the Silicide:
An integrated process that prevents melting or agglomeration of the nickel silicide contact during DSA is described with reference to
The next step (block 350 of
The metal silicide contacts 265 formed in the sequence of
The mixture of a higher melting temperature metal (e.g., Ti and/or Co) with the Ni in the silicide compound of the contact 265 renders the contact less susceptible or more impervious to melting or agglomeration at the high temperature of the DSA process step. The proportion of the Ti and/or Co in the nickel silicide material should be sufficiently high to achieve this result but not so high as to compromise the low resistance qualities of the nickel silicide for small line widths (e.g., less than 45 nm). Generally, the proportion of Ni is twice the proportion of either Ti or Co.
Following completion of the contact formation process of
Integrated Process with Prevention of Contact Silicide Agglomeration During DSA Using a Mechanically Compressive Cap:
An integrated circuit fabrication process that prevents agglomeration of the nickel silicide contact during DSA using physical compression is described with reference to
The first step in this process (block 400 of
In an alternative embodiment, the process of
Another mode for imposing a mechanically compressive layer on the nickel silicide contacts 265 is to deposit the etch stop and PMD layers 272, 284 of
While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims
1. A method of processing a substrate having a silicon-containing semiconductor channel and an overlying silicon-containing gate electrode separated from said channel by a thin gate dielectric layer, comprising:
- forming a pair of source-drain regions in said channel adjacent opposing edges of said gate electrode by ion implanting dopant impurities;
- depositing a metal-containing layer on top surfaces of said sourcedrain regions and of said gate electrode;
- performing a rapid thermal process step to heat said substrate sufficiently to form metal silicide contacts at the top surfaces of said sourcedrain regions and of said gate electrode;
- removing the remainder, of said metalcontaining layer;
- forming an etch stop layer over said substrate so as to cover top surfaces of said source-drain regions and of said gate electrode with said etch stop layer;
- depositing an optical absorber layer over said etch stop layer;
- scanning a focused line beam of radiation from an array of plural lasers across said substrate along a direction transverse to the focused line beam so as to create a surface temperature near the melting point of said substrate in a surface zone illuminated by the line beam; and
- removing said optical absorber layer.
2. The method of claim 1 wherein said metal containing layer comprises nickel.
3. The method of claim 2 wherein said rapid thermal process step heats said substrate to a temperature of about 450° C.
4. The method of claim 1 wherein depositing a metal-containing, layer comprises:
- depositing a base metal layer of nickel;
- depositing on said base metal layer an overlying layer of a metal having a higher melting temperature than nickel.
5. The method of claim 4 wherein said overlying metal layer comprises one of: (a) titanium, (b) cobalt.
6. The method of claim 5 further comprising depositing on said overlying layer a second overlying layer of the other one of: (a) titanium, (b) cobalt.
7. The method of claim 6 wherein said base layer is on the order of about two times more thick than each one of said overlying layer and second overlying layer.
8. The method of claim 4 wherein said base layer is on the order of about two times more thick than said overlying layer.
9. The method of claim 8 wherein said base layer is about 100 nm thick and said overlying layer is about 50 nm thick.
10. The method of claim 8 wherein said base layer is about 100 nm thick, said overlying layer is about 50 nm thick and said second overlying layer is about 50 nm thick.
11. The method of claim 1 further comprising:
- after removing said, optical absorber layer, depositing a pre-metal dielectric layer on said etch stop layer;
- performing a first dielectric etch process so as to form respective contact openings through said pre-metal dielectric layer in registration with respective ones of said contacts, wherein said etch stop layer comprises a material having a lower etch rate than said pre-metal dielectric layer in said first etch process; and
- performing a second dielectric etch process so as to form respective contact openings through said etch stop layer.
12. The method of claim 1 further comprising:
- prior to depositing the optical absorber layer, depositing a pre-metal dielectric layer on said etch stop layer, whereby said optical absorber layer is deposited on said pre-metal dielectric layer;
- after removing the optical absorber layer, performing a first dielectric etch process so as to form respective contact openings through said pre-metal dielectric layer in registration with respective ones of said contacts, wherein said etch stop layer comprises a material having a lower etch rate than said pre-metal dielectric layer in said first etch process; and
- performing a second dielectric etch process so as to form respective contact openings through said etch stop layer.
13. The method of claim 12 wherein depositing a metal-containing layer comprises:
- depositing a base metal layer of nickel;
- depositing on said base metal layer an overlying layer of a metal having a higher melting temperature than nickel.
14. The method of claim 13 wherein said overlying metal layer comprises one of: (a) titanium, (b) cobalt.
15. The method of claim 14 further comprising depositing on said overlying layer a second overlying layer of the other one of: (a) titanium, (b) cobalt.
16. The method of claim 15 wherein said base layer is on the order of about two times more thick than each one of said overlying layer and second overlying layer.
17. The method of claim 16 wherein said base layer is about 100 nm thick, said overlying layer is about 50 nm thick and said second overlying layer is about 50 nm thick.
18. The method of claim 13 wherein said base layer is on the order of about two times more thick than said overlying layer.
19. The method of claim 18 wherein said base layer is about 100 nm thick and said overlying layer is about 50 nm thick.
20. The method of claim 1 further comprising:
- prior to depositing the etch stop layer, depositing a compression layer on said substrate, said compression layer being of sufficient thickness to retard or prevent agglomeration of the metal suicide material of said contacts during the scanning of the focused line beam of laser radiation.
21. The method of claim 20 wherein said compression layer comprises silicon nitride.
22. The method of claim 21 wherein said compression layer is on the order of about 3000 Å to 8000 Å thick.
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Type: Grant
Filed: Aug 9, 2007
Date of Patent: Jun 15, 2010
Patent Publication Number: 20090042376
Assignee: Applied Materials, Inc. (Santa Clara, CA)
Inventors: Yi Ma (Santa Clara, CA), Philip Allan Kraus (San Jose, CA), Christopher Sean Olsen (Fremont, CA), Khaled Z. Ahmed (Anaheim, CA), Abhilash J. Mayur (Salinas, CA)
Primary Examiner: Zandra Smith
Assistant Examiner: Christy L Novacek
Attorney: Law Office of Robert M. Wallace
Application Number: 11/836,267
International Classification: H01L 21/44 (20060101);