Abstract: A ring configurator for interconnection of data processing and communication systems uses fully covered rings. The ring configuration mechanism can be used to construct a set of covering rings preserving full connectivity for system interconnect. The mechanism can also be used for establishing the routing table for each interconnected system during the system initialization time. To generate a set of edge-disjoint rings, a rotational mechanism is used. The rings are considered stretching along a horizontal direction with nodes aligned in columns across all the rings. With a proper relabeling of the nodes, nodes appearing in the same column position of each ring can be obtained by a simple rotation of the nodes from the previous column of the rings. Once the rotational position is determined for each column, a set of N-1 edge-disjoint rings can be constructed. To find an extra ring so that when combined with the N-1 rings thus found the ring constraints are satisfied, a node reduction technique is invoked.

Abstract: A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

Abstract: A packet switch system having a buffer occupancy reduction mechanism for controlling data flow through switched nodes of the system to avoid congestion and reduce required buffer storage at the nodes. For an isochronous connection, buffers are initially allocated at each switching node connection to ensure listless transmission of packets. A buffer occupancy trace for the connection is recorded and the delay time of an isochronous packet at a particular switch port is returned to a preceding switch port. The preceding switch port employs the feedback message to delay subsequent packets through the connection to reduce the queuing time at the particular switch port. Once the isochronous connection has stabilized, buffer reallocation is performed wherein a scheduler at each switch node along the connection attempts to combine buffer allocations for different isochronous connections. This occurs provided the corresponding buffer occupancy traces of the isochronous connections do not overlap.

Abstract: A method and apparatus for intermixing circuit and packet data on a shared transmission medium. With this invention, the history of gaps between transmitted circuit frames is used to predict future gap sizes. If the size of a predicted gap is larger than the size of a frame of packet data to be transmitted, then the packet data is inserted in the next gap. If a circuit data frame arrives before the completion of transmission of a packet frame, the circuit data will be stored in an insertion buffer until completion of transmission of the packet frame.

Abstract: Switch resources for a one-sided crosspoint switch with distributed control (i.e., switch ports, internal busses and controllers) have been organized so that modular growth is facilitated by: (1) assigning each switch port uniquely to one of the controllers; (2) making each controller handle only the crosspoints connected to the switch ports assigned to it; (3) assigning each internal bus uniquely to one of the controllers; and (4) providing a network for the controllers to communicate with each other.

Abstract: A hybrid local area network (LAN) for the interconnection of multiple stations. The LAN consists of an N-port non-blocking switch and multiple subnetworks interconnected via passive optical couplers. Each station in the system is attached via a duplex fiber-optic link, either directly to a switch port or to a subnetwork, which in turn, is attached to a switch port. A subnetwork is interconnected by means of a passive optical combiner (incoming lines to the switch port) and a passive optical splitter (outgoing lines from switch port). The LAN is structured in a way that minimizes the delay incurred for communications between the subnetworks. The LAN protocol allows for any-to-any interconnections, multiple simultaneous transmissions, and broadcasting.

Abstract: A partitioned switch having distributed clocks includes a global matrix switch and one or more self-contained mini-switches. The mini-switches each contain ports connected via a local matrix switch. Communication between ports located in the same mini-switch is performed synchronously and in parallel via the local matrix switch. Communication between ports located in different mini-switches is performed asynchronously and serially via the global matrix switch. The mini-switches control the global matrix switch by serially and asynchronously sending control information to the global matrix switch.

Abstract: Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume.

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

Abstract: In a one-sided crosspoint switch, multiple controllers are used instead of a single controller for control of the switching matrix. The controllers operate in parallel, thereby handling requests for connections and disconnections from ports at a higher speed than with a single controller. In the event of a controller failure, the remaining controllers also take over the control function of the failed controller, thereby providing improved reliability.

Abstract: An improved multiplex controller circuit allows fast, on demand allocation of variable length time slots in a voice/data communications system. The controller circuit directly maps a triangular connection matrix into hardware, thereby providing hardware parallelism Each one of the coordinate points of the matrix is implemented with a flip-flop (L.sub.ij). The inputs of the flip-flops are provided by a Port Activity Register (PAR), and the outputs of the flip-flops are fed into a Priority Encoder circuit (PE) which generates the address of a switch adapter with which a connection can be established. In this manner, a high speed dynamic allocator of variable length time slots which solves controller bottleneck problems in time critical systems is realized.

Abstract: A hierarchy of multipath networks selectively provides connections between a plurality of sources and a plurality of destinations in a communications system. The hierarchy comprises a first multipath network without buffering which consists of two or more stages and constituting a fast path for connecting a source to a destination. At least a second multipath network with buffering and comprising a plurality of stages constitutes an alternate, slower path for connecting a source to a destination in the event that a connection between the source and the destination is blocked in the fast path. The address field of a message from a source is examined at each stage to select an appropriate connection to the next stage and, if the connection is available, the message, stripped of the address field, is propagated to the second stage, but if the next stage is blocked, the message is stopped and a negative acknowledgment is returned to the source.

Abstract: A high speed collision N.times.M tri-state crossbar switch having M collision busses uses contention detection at the destination. In the event of a collision of messages, remedial action can be taken such as rerouting colliding messages over an alternate path provided by a second interconnection network with contention resolution capability. Collision detection codes are transmitted prior to the transmission of messages to each input port. The tri-state output buses are monitored for the collison detection codes to detect an error. In order to prevent damage to driver transistors connected to the tri-state buses when a contention occurs, current limiting is provided to limit the current through the driver transistors to a predetermined level.

Abstract: The invention provides a crosspoint switching system (30) comprising a plurality of switching planes for transferring data therethrough. The switching planes are comprised of two types, data planes (32) used only for transferring data between processors and at least one control/data plane (34) capable of transferring data and controlling crosspoints in the other data planes. The switching system is operable with two protocols, a message-switched mode in which only the control/data plane is used for transfer of data and a circuit-switched mode in which the control/data plane and the other data planes are used for transfer of data.

Abstract: A cross-point switching array in which each cross-point of the array is controlled by the output of a first memory. Each first memory is associated with a second memory. The second memories can be sequentially set by a single controller while the cross-point connections are maintained according to the first memories. The contents of all second memories are concurrently loaded into the associated first memories to simultaneously reconfigure the cross-point array.

Abstract: A memory system backup for use in a tightly or loosely coupled multiprocessor system. A plurality of primary memory units having substantially the same configuration are backed up by a single memory unit of similiar configuration. The backup memory unit holds the checksum of all data held in all primary memory units. In the event of the failure of one of the primary memory units its contents can be recreated based on the data in the remaining non-failed memory unit and the checksum in the backup unit.

Abstract: A method of integrating the switching of voice and data between terminals connected to switch adapters. The switching of voice (or more generally synchronous signals) is accomplished by grouping voice samples in a first adapter and bound for the same destination or second adapter into a frame. Connections are then established between the two adapters and the frame is transmitted therethrough. A duplex method can also be set up by transmitting in both directions at the same time once a dual connection between the first and second adapter is established. Hence, a second group of voice samples bound for the first adapter is also formed ina frame. The two frames are then transmitted simultaneously in opposite directions through a dual connection in the switching matrix. Data is switched by storing data in respective memories of respective adapters, wherein each respective memory corresponds to a particular adapter to which the data stored therein is to be sent.

Abstract: A switching apparatus and adjustable time delay protocol to provide switching between N processor system devices in which each device is connected via N+S fibers to N+S switching planes, with one fiber being used for the connection from a device to one of the N+S switching planes. N fibers provide the desired bandwidth and S fibers are used as standby fibers in the event of failure of any of the N fibers. An additional C fiber from each device to a single matrix controller are used to provide control information. The single controller provides control for all N+S switching planes. Each switching plane converts the optical signals that are received over M fibers to electrical signals. The electrical signals are then switched and converted to optical signals by the respective switching planes. Thus, each of the optical signals received over each of the M fibers are transmitted to a respective other one of the M fibers.

Abstract: A full-duplex one-sided switching chip comprising externally connected lines as input/output pairs and pairs of bi-directional interconnection lines. Duplex cross-points selectively connect input/output line pairs to the interconnection line pairs. The interconnection lines can be coupled to interconnection lines on other chips for multichip switching arrays.

Abstract: A method of arbitrating for N processors requesting access to a shared resource utilizing 2 log.sub.2 N shared variables, such as electrical lines. Each processor can assert a line which is asserted if any processor is asserting it. A requesting processor asserts one of two lines for each bit of a unique processor address, the choice of line depending on the value of the bit. The processor then examines the non-asserted line to determine if it is asserted by another processor. If the other line is asserted, the requesting processor either releases its own asserted line or waits depending on the value of the address bit. Thus, priority is determined by the address values. Once a processor has successfully asserted lines for every bit of its address it is granted access.Arbitration with fairness can be obtained by dividing processors into two fairness groups and assigning a turn to one of the groups. A processor is allowed into arbitration if the turn belongs to its fairness group.