Patents by Inventor Christos VEZYRTZIS

Christos VEZYRTZIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10666415
    Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phillip John Restle, Christos Vezyrtzis, James Douglas Warnock
  • Patent number: 10652006
    Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phillip John Restle, Christos Vezyrtzis, James Douglas Warnock
  • Publication number: 20200110656
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Patent number: 10552250
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Publication number: 20200019224
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: August 14, 2019
    Publication date: January 16, 2020
    Inventors: Pierce I-Jen Chuang, Phillip J. Restle, Christos Vezyrtzis, Divya Pathak
  • Patent number: 10437311
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pierce I. Chuang, Divya Pathak, Phillip J. Restle, Christos Vezyrtzis
  • Patent number: 10333520
    Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
  • Publication number: 20190146568
    Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
  • Patent number: 10261561
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pierce I. Chuang, Phillip J. Restle, Christos Vezyrtzis
  • Publication number: 20190108087
    Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 11, 2019
    Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
  • Patent number: 10230360
    Abstract: The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christos Vezyrtzis, Pawel Owczarczyk
  • Publication number: 20190036530
    Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.
    Type: Application
    Filed: December 14, 2017
    Publication date: January 31, 2019
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
  • Patent number: 10171081
    Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
  • Publication number: 20180367128
    Abstract: The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 20, 2018
    Inventors: Christos Vezyrtzis, Pawel Owczarczyk
  • Patent number: 10145892
    Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 4, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, COMPUTER TASK GROUP, INC.
    Inventors: Robert L. Franch, Phillip J. Restle, Thomas Strach, Christos Vezyrtzis, Scott F. Warnock
  • Publication number: 20180198596
    Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.
    Type: Application
    Filed: December 14, 2017
    Publication date: July 12, 2018
    Inventors: Phillip John Restle, Christos Vezyrtzis, James Douglas Warnock
  • Publication number: 20180198595
    Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventors: Phillip John Restle, Christos Vezyrtzis, James Douglas Warnock
  • Publication number: 20180067541
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: PIERCE I. CHUANG, PHILLIP J. RESTLE, CHRISTOS VEZYRTZIS
  • Publication number: 20180067532
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: PIERCE I. CHUANG, DIVYA PATHAK, PHILLIP J. RESTLE, CHRISTOS VEZYRTZIS
  • Publication number: 20180052200
    Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: ROBERT L. FRANCH, PHILLIP J. RESTLE, THOMAS STRACH, CHRISTOS VEZYRTZIS, SCOTT F. WARNOCK