Patents by Inventor Christos VEZYRTZIS
Christos VEZYRTZIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11693728Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: February 11, 2022Date of Patent: July 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11671079Abstract: Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.Type: GrantFiled: November 17, 2021Date of Patent: June 6, 2023Assignee: Bitmain Development Inc.Inventors: Christos Vezyrtzis, Peter Holm, Stephen M. Beccue
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Publication number: 20230155576Abstract: Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.Type: ApplicationFiled: November 17, 2021Publication date: May 18, 2023Applicant: Bitmain Development Inc.Inventors: Christos Vezyrtzis, Peter Holm, Stephen M. Beccue
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Patent number: 11561595Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.Type: GrantFiled: June 25, 2021Date of Patent: January 24, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
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Publication number: 20220352879Abstract: Embodiments of the invention provide for a dynamic pulse generator which can combine both the sequential element and the pulse logic into one stage, thereby eliminating the wasted time resulting from a pulse generator' input-to-output propagation delay. The dynamic pulse generator can include a plurality of P-MOS an N-MOS transistors, a first delay element, and a second delay element.Type: ApplicationFiled: April 30, 2021Publication date: November 3, 2022Applicant: Bitmain Development Inc.Inventors: Christos Vezyrtzis, Peter Holm, Steve Beccue
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Publication number: 20220349938Abstract: Embodiments of the invention provide for integrated circuits for testing one or more transistors for process variation effects. According to an embodiment, the integrated circuit can include: a plurality of ring oscillator macro circuits, wherein each ring oscillator macro circuit includes two ring oscillators, a first multiplexer, and a first divide-by-two circuit; a multiplexer stage; a divide-by-two circuit stage; a second multiplexer; a second divide-by-two circuit; and frequency measurement circuit. According to another embodiment, the integrated circuit can include: a first shift register including a plurality of devices-under-test; a second shift register including a plurality of static latches; a first multiplexer configured to receive outputs from each of the plurality of DUTs; a second multiplexer configured to receive outputs from each of the plurality of static latches; and a comparator configured to compare an output from the first multiplexer with an output from the second multiplexer.Type: ApplicationFiled: April 30, 2021Publication date: November 3, 2022Applicant: Bitmain Development Inc.Inventors: Christos Vezyrtzis, Peter Holm, Steve Beccue
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Publication number: 20220164250Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: ApplicationFiled: February 11, 2022Publication date: May 26, 2022Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 11309874Abstract: Power dissipation of sequential static latch, implemented in CMOS, may be reduced by removing clocked elements from the circuit. One way to do this may be to replace a clocked digital feedback path with an analog programmable feedback path. An analog programmable feedback path, such as disclosed, may, for example, provide a constant, non-clocked bias by providing constant bias voltages to transistors in the feedback path such that they function as analog devices rather than digital switches. This bias may be adjusted, e.g., to reflect the circuit's operating environment.Type: GrantFiled: April 30, 2021Date of Patent: April 19, 2022Assignee: Bitmain Development Inc.Inventors: Christos Vezyrtzis, Peter Holm, Steve Beccue
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Patent number: 11275644Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: December 6, 2019Date of Patent: March 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Publication number: 20220075435Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.Type: ApplicationFiled: June 25, 2021Publication date: March 10, 2022Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
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Patent number: 11073884Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.Type: GrantFiled: November 15, 2017Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis
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Patent number: 11036276Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.Type: GrantFiled: August 14, 2019Date of Patent: June 15, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pierce I-Jen Chuang, Phillip J. Restle, Christos Vezyrtzis, Divya Pathak
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Patent number: 10666415Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.Type: GrantFiled: January 6, 2017Date of Patent: May 26, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Phillip John Restle, Christos Vezyrtzis, James Douglas Warnock
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Patent number: 10652006Abstract: Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.Type: GrantFiled: December 14, 2017Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Phillip John Restle, Christos Vezyrtzis, James Douglas Warnock
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Publication number: 20200110656Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: ApplicationFiled: December 6, 2019Publication date: April 9, 2020Inventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Patent number: 10552250Abstract: Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.Type: GrantFiled: October 10, 2017Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Giora Biran, Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Preetham M. Lobo, Ramon Bertran Monfort, Phillip John Restle, Christos Vezyrtzis, Tobias Webel
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Publication number: 20200019224Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.Type: ApplicationFiled: August 14, 2019Publication date: January 16, 2020Inventors: Pierce I-Jen Chuang, Phillip J. Restle, Christos Vezyrtzis, Divya Pathak
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Patent number: 10437311Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.Type: GrantFiled: September 6, 2016Date of Patent: October 8, 2019Assignee: International Business Machines CorporationInventors: Pierce I. Chuang, Divya Pathak, Phillip J. Restle, Christos Vezyrtzis
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On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core
Patent number: 10333520Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.Type: GrantFiled: December 14, 2017Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis -
Publication number: 20190146568Abstract: Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.Type: ApplicationFiled: November 15, 2017Publication date: May 16, 2019Inventors: Pradip Bose, Alper Buyuktosunoglu, Pierce I-Jen Chuang, Phillip John Restle, Christos Vezyrtzis