Patents by Inventor Christos VEZYRTZIS

Christos VEZYRTZIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9829535
    Abstract: An integrated circuit includes a test block which in turn includes a plurality of identical paths; a counter selectively coupled to the plurality of identical paths to selectively obtain a count of at least one of correctly operating paths and incorrectly operating paths from each of the plurality of identical paths; and a plurality of count latches selectively coupled to the counter to store output of the counter. Each path in turn includes a first clocked latch; a clocked logic path beginning and ending at the first clocked latch; and a clocked detection circuit coupled to the first clocked latch and the counter, which determines whether the clocked logic path is operating properly in a given clock period.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: November 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Bruce M. Fleischer, Keith A. Jenkins, Christos Vezyrtzis
  • Patent number: 9702924
    Abstract: A structure and method of testing degradation of semiconductor devices by stressing an array of several semiconductor devices at the same time and measuring the resulting degradation separately for each individual device to obtain an estimate of its expected lifetime is provided. The devices may be subjected to stress that is either in a pulsed state or in a DC state. An on-chip pulse generator may be used for stressing in the pulsed state.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Keith A. Jenkins, Christos Vezyrtzis
  • Patent number: 9618966
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Patent number: 9612614
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Publication number: 20170031383
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Publication number: 20170031384
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Application
    Filed: August 18, 2015
    Publication date: February 2, 2017
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Publication number: 20160341785
    Abstract: A structure and method of testing degradation of semiconductor devices by stressing an array of several semiconductor devices at the same time and measuring the resulting degradation separately for each individual device to obtain an estimate of its expected lifetime is provided. The devices may be subjected to stress that is either in a pulsed state or in a DC state. An on-chip pulse generator may be used for stressing in the pulsed state.
    Type: Application
    Filed: May 19, 2015
    Publication date: November 24, 2016
    Inventors: Karthik Balakrishnan, Keith A. Jenkins, Christos Vezyrtzis
  • Publication number: 20160209467
    Abstract: An integrated circuit includes a test block which in turn includes a plurality of identical paths; a counter selectively coupled to the plurality of identical paths to selectively obtain a count of at least one of correctly operating paths and incorrectly operating paths from each of the plurality of identical paths; and a plurality of count latches selectively coupled to the counter to store output of the counter. Each path in turn includes a first clocked latch; a clocked logic path beginning and ending at the first clocked latch; and a clocked detection circuit coupled to the first clocked latch and the counter, which determines whether the clocked logic path is operating properly in a given clock period.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 21, 2016
    Inventors: Karthik Balakrishnan, Bruce M. Fleischer, Keith A. Jenkins, Christos Vezyrtzis
  • Patent number: 8788277
    Abstract: Apparatus and methods for processing compression encoded signals are provided. In some embodiments, a signal processing method is provided that includes receiving a subband of a compression encoded signal at a subband processor, generating envelope information regarding the subband of the compression encoded signal to provide changes in the dynamic range of the compression encoded signal for fixed-point digital signal processing, processing the compression encoded signal with a fixed-point companding digital signal processor using the envelope information, and producing a processed compression encoded signal at the output of the subband processor.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 22, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Christos Vezyrtzis, Aaron Klein, Yannis Tsividis, Daniel P. W. Ellis
  • Publication number: 20110116551
    Abstract: Apparatus and methods for processing compression encoded signals are provided. In some embodiments, a signal processing method is provided that includes receiving a subband of a compression encoded signal at a subband processor, generating envelope information regarding the subband of the compression encoded signal to provide changes in the dynamic range of the compression encoded signal for fixed-point digital signal processing, processing the compression encoded signal with a fixed-point companding digital signal processor using the envelope information, and producing a processed compression encoded signal at the output of the subband processor.
    Type: Application
    Filed: September 13, 2010
    Publication date: May 19, 2011
    Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Christos VEZYRTZIS, Aaron KLEIN, Yannis TSIVIDIS, Daniel P.W. ELLIS