Patents by Inventor Christy Mei-Chu Woo

Christy Mei-Chu Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7994047
    Abstract: An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: August 9, 2011
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Ning Cheng, Huade Walter Yao
  • Patent number: 7755194
    Abstract: A composite ?-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an ?-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 ? to about 50 ?. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the N2 flow rate and/or ratio of the thickness of the combined ?-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: July 13, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit Marathe, Connie Pin-Chin Wang, Christy Mei-Chu Woo, Paul L. King
  • Patent number: 7157795
    Abstract: Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of ?-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: January 2, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Steven C. Avanzino, Christy Mei-Chu Woo
  • Patent number: 7071564
    Abstract: The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of ?-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the ?-Ta layer and a layer of ?-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of ?-Ta at a thickness of 25 ? to 40 ?, depositing a layer of tantalum nitride at a thickness of 20 ? to 100 ? and then depositing a layer of ?-Ta at a thickness of 200 ? to 500 ?. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with ?-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Darrell M. Erb, Steven Avanzino, Christy Mei-Chu Woo
  • Patent number: 7045384
    Abstract: A method of determining a work function of a metal to be used as a metal gate material provides a metal-on-silicon (MS) Schottky diode on a silicon substrate. The MS Schottky diode is formed by deposition of the metal in a single step deposition through a shadow mask that is secured on the silicon substrate.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: May 16, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James N. Pan, Christy Mei-Chu Woo
  • Patent number: 7033940
    Abstract: A composite ?-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a controlled surface roughness for improved adhesion, electromigration resistance and reliability. Embodiments include lining a damascene opening, such as a dual damascene opening in a low-k interlayer dielectric, with an initial layer of TaN, forming a graded tantalum nitride layer on the initial TaN layer and then forming an ?-Ta layer on the graded TaN layer, the composite barrier layer having an average surface roughness (Ra) of about 25 ? to about 50 ?. Embodiments further include controlling the surface roughness of the composite barrier layer by varying the N2 flow rate and/or ratio of the thickness of the combined ?-Ta and graded tantalum nitride layers to the thickness of the initial TaN layer.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit Marathe, Connie Pin-Chin Wang, Christy Mei-Chu Woo, Paul L. King
  • Patent number: 6989604
    Abstract: An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 24, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Minh Van Ngo, John E. Sanchez, Jr., Steven C. Avanzino
  • Patent number: 6979625
    Abstract: High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the relatively wider openings. The filled openings are recessed and a metal capping layer deposited followed by CMP. The metal capping layer prevents diffusion along the copper-capping layer interface while the copper alloy filling the relatively wider openings impedes electromigration along the grain boundaries.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 27, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Connie Pin-Chin Wang, Darrell M. Erb
  • Patent number: 6952052
    Abstract: A composite ?-Ta/ graded tantalum nitride /TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous ?-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of ?-Ta, e.g., as at a thickness of bout 50 ? to about 100 ?. Embodiments include composite barrier layers having a thickness ratio of ?-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: October 4, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit P. Marathe, Connie Pin-Chin Wang, Christy Mei-Chu Woo
  • Patent number: 6939803
    Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: September 6, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit P. Marathe, Pin-Chin Connie Wang, Christy Mei-Chu Woo
  • Patent number: 6893910
    Abstract: A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: May 17, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Paul R. Besser, Minh Van Ngo, James N. Pan, Jinsong Yin
  • Patent number: 6861350
    Abstract: Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 ? to 75 ?, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: March 1, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Jinsong Yin, James Pan, Paul R. Besser
  • Patent number: 6836017
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: December 28, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Jr., Suzette K. Pangrle
  • Patent number: 6830998
    Abstract: Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: December 14, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Pan, Paul Besser, Christy Mei-Chu Woo, Minh Van Ngo, Jinsong Yin
  • Patent number: 6806172
    Abstract: Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: October 19, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Eric N. Paton, Susan Tover
  • Publication number: 20040147117
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Suzette K. Pangrle
  • Patent number: 6730587
    Abstract: Nickel silicidation of a gate electrode is controlled using a titanium barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of titanium thereon and an upper polycrystalline silicon layer on the titanium layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and a titanium silicide barrier layer is formed preventing nickel from reacting with the lower polycrystalline silicon layer.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: May 4, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jacques J. Bertrand, Christy Mei-Chu Woo, Minh Van Ngo, George Kluth
  • Patent number: 6727592
    Abstract: A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of &agr;-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin &agr;-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: April 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, John E. Sanchez, Darrell M. Erb, Amit P. Marathe
  • Patent number: 6724051
    Abstract: A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Minh Van Ngo, George Jonathan Kluth
  • Patent number: 6723635
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Jr., Suzette K. Pangrle