Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

Abstract: A method to fabricate interconnect structures that are part of integrated circuits and microelectronic devices by utilization of an irradiation to remove and clean a sacrificial material used therein is described. The advantages of utilizing the irradiation to remove the sacrificial material include reduced damage to interlayer dielectric layers that result in enhanced device performance and/or increased reliability.

Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

Abstract: A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

Abstract: A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

Abstract: A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

Abstract: An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

Abstract: A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, 0?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

Abstract: A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

Abstract: A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

Abstract: An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

Abstract: A method for removing a dielectric layer formed upon a semiconductor substrate is disclosed. In an exemplary embodiment of the invention, the method includes subjecting the dielectric layer to a dry etch process and subjecting an adhesion promoter layer underneath the dielectric layer to a wet etch process.

Abstract: An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

Abstract: A crosslinked polyarylene material with a reduced coefficient of thermal expansion at high temperatures compared with conventional crosslinked polyarylene materials is provided. In addition, an integrated circuit article containing a crosslinked polyarylene polymer with reduced coefficient of thermal expansion at high temperatures is provided.