Patents by Inventor Chrong-Jung Lin

Chrong-Jung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210313472
    Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Patent number: 11043601
    Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Publication number: 20210159129
    Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Inventors: Burn-Jeng LIN, Chrong-Jung LIN, Ya-Chin KING, Yi-Pei TSAI
  • Patent number: 10910469
    Abstract: A semiconductor device includes a substrate and a conducting structure. The substrate has a first conductivity type and includes a first isolation region, a first implant region, and a second implant region. The first isolation region is disposed along the circumference of the substrate. The first implant region has the first conductivity type, and the second implant region has a second conductivity type that is the opposite of the first conductivity type. The conducting structure is disposed on the substrate, and at least a portion of the conducting structure is located on the first isolation region.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: February 2, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hua Wen, Chia-Shen Liu, Wen-Chung Chen, Chrong-Jung Lin
  • Publication number: 20200395411
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
  • Publication number: 20200388676
    Abstract: A semiconductor device includes a substrate and a conducting structure. The substrate has a first conductivity type and includes a first isolation region, a first implant region, and a second implant region. The first isolation region is disposed along the circumference of the substrate. The first implant region has the first conductivity type, and the second implant region has a second conductivity type that is the opposite of the first conductivity type. The conducting structure is disposed on the substrate, and at least a portion of the conducting structure is located on the first isolation region.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hua WEN, Chia-Shen LIU, Wen-Chung CHEN, Chrong-Jung LIN
  • Publication number: 20200321255
    Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.
    Type: Application
    Filed: September 26, 2019
    Publication date: October 8, 2020
    Inventors: Burn-Jeng LIN, Chrong-Jung LIN, Ya-Chin KING, Yi-Pei TSAI
  • Patent number: 10763305
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Woan-Yun Hsiao, Huang-Kui Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong-Jung Lin
  • Publication number: 20190252552
    Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Patent number: 10276726
    Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Patent number: 10269437
    Abstract: A non-volatile memory device including a first floating-gate element, a second floating-gate element, and a selection gate element. The first floating-gate element includes a gate electrode configured to generate a read current based on the read voltage, the control voltage, and the electrical state of the gate electrode. The second floating-gate element shares a gate electrode with the first floating-gate element and is configured to determine the electrical state of the gate electrode based on the write voltage and the control voltage. The selection gate element is electrically coupled to the first floating-gate element and the second floating-gate element and is configured to generate the control voltage according to the word driving voltage and the source driving voltage.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 23, 2019
    Assignee: Copee Technology Company
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Publication number: 20190035850
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.
    Type: Application
    Filed: September 18, 2018
    Publication date: January 31, 2019
    Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
  • Publication number: 20180315481
    Abstract: A non-volatile memory device including a first floating-gate element, a second floating-gate element, and a selection gate element. The first floating-gate element includes a gate electrode configured to generate a read current based on the read voltage, the control voltage, and the electrical state of the gate electrode. The second floating-gate element shares a gate electrode with the first floating-gate element and is configured to determine the electrical state of the gate electrode based on the write voltage and the control voltage. The selection gate element is electrically coupled to the first floating-gate element and the second floating-gate element and is configured to generate the control voltage according to the word driving voltage and the source driving voltage.
    Type: Application
    Filed: March 19, 2018
    Publication date: November 1, 2018
    Inventors: Chrong-Jung LIN, Ya-Chin KING
  • Patent number: 10090360
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Woan-Yun Hsiao, Ya-Chin King, Chrong-Jung Lin, Huang-Kui Chen, Tzong-Sheng Chang
  • Publication number: 20170345941
    Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Jiun Shiung Wu, Ya-Chin King, Chrong-Jung Lin
  • Patent number: 9831130
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: An-Lun Lo, Wei-Shuo Ho, Tzong-Sheng Chang, Chrong-Jung Lin, Ya-Chin King
  • Patent number: 9805796
    Abstract: A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current, so as to generate a data-stored state signal.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 31, 2017
    Assignee: Copee Technology Company
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Publication number: 20170278570
    Abstract: A non-volatile memory device includes a first floating gate unit, a second floating gate unit, a selecting gate unit and a comparator. The first floating gate unit is configured to generate a first current according to a first bit signal and a control electric potential. The second floating gate unit is connected with the first floating gate unit in parallel, and configured to generate a second current according to a second bit signal and the control electric potential. The selecting gate unit is connected to the first floating gate unit and the second floating gate unit, and configured to generate the control electric potential according to a source signal and a word signal. The comparator is electrically connected to the first floating gate unit and the second floating gate unit, and configured to compare the first current with the second current, so as to generate a data-stored state signal.
    Type: Application
    Filed: February 20, 2017
    Publication date: September 28, 2017
    Inventors: Chrong-Jung LIN, Ya-Chin KING
  • Publication number: 20170278756
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: An-Lun LO, Wei-Shuo HO, Tzong-Sheng CHANG, Chrong-Jung LIN, Ya-Chin KING
  • Patent number: 9679818
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 13, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Lun Lo, Wei-Shuo Ho, Tzong-Sheng Chang, Chrong-Jung Lin, Ya-Chin King