Abstract: An integrated circuit device includes a first metallization layer, a second metallization layer, and a first metal via. The first metallization layer comprises two adjacent first metal lines. The second metallization layer is over the first metallization layer, wherein the second metallization layer comprises a second metal line. The first metal via is connected with a bottom of the second metal line. The first metal via is between the first metal lines and misaligned with the first metal lines in a top view.

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Abstract: A device includes a detector transistor, a sensing pad, a first conductive ring, a second conductive ring, a first transistor, and a second transistor. The sensing pad is over the detector transistor. The first conductive ring is over the sending pad. The second conductive ring is over the first conductive ring. The first transistor has a source/drain region electrically coupled to the first conductive ring. The second transistor has a source/drain region electrically coupled to the second conductive ring.

Abstract: A three-dimensional resistive random access memory structure includes a base layer, a first layer, a second layer, a third layer and a fourth layer. The first layer includes two first conductive layers and a first via. One of the two first conductive layers is electrically connected between the base layer and the first via. The second layer includes three second conductive layers and two second vias. Two first resistive elements are formed between one of the two second vias and two of the three second conductive layers. The third layer includes three third conductive layers and two third vias. Two second resistive elements are formed between one of the two third vias and two of the three third conductive layers. The fourth layer includes a fourth conductive layer. The fourth conductive layer is electrically connected to the two third vias.

Abstract: A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Abstract: A fabricating method of a resistive random access memory unit with one-way conduction characteristic includes performing an initializing step, a forming step and a reverse resetting step. The initializing step includes providing the resistive random access memory unit. The forming step includes applying a setting voltage on a lower metal layer, and coupling an upper metal layer to a ground voltage to transform the resistive random access memory unit to a low resistive state. The reverse resetting step includes coupling the lower metal layer to the ground voltage and applying a resetting voltage to the upper metal layer to transform the resistive random access memory unit to a one-way conduction state. A forward reading current is greater than a reverse reading current, and the forward reading current is less than 3000 times of the reverse reading current.

Abstract: A semiconductor device includes a sensing element including a sensing electrode and a filter covering the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is over the sensing electrode. The second work function layer is over the first work function layer. A work function value of the second work function layer is greater than a work function value of the first work function layer, and an atomic percentage of metal in the second work function layer is greater than an atomic percentage of metal in the first work function layer.

Abstract: A The memory device includes a memory array comprising a plurality of one-time-programmable (OTP) memory cells. Each of the plurality of OTP memory cells comprises: a select transistor; a diode; and a conductor fuse. The diode and the conductor fuse are coupled in series, with the select transistor coupled to a common node between the diode and the conductor fuse.

Abstract: A device in a chamber is provided. The device comprises at least one die. The at least one die comprise a first voltage generator, a dielectric layer and a first voltage regulator circuit. The first voltage generator is charged to have a first induced voltage by induced charges generated in response to a first voltage of a first electrode of a chuck in the chamber. The dielectric layer surrounds the first voltage generator to isolate the first voltage generator from the first electrode. The first voltage regulator circuit is coupled to the first voltage generator to receive the first induced voltage and generates a first power supply voltage according to the first induced voltage for a first circuit in the device.

Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Abstract: A semiconductor structure includes a substrate, a semiconductor detector, a peripheral circuit, and a multilayer interconnection structure. The substrate has a sensing region and a peripheral region. The semiconductor detector is on the sensing region of the substrate. The semiconductor detector includes a first detector unit, a second detector unit, and a third detector unit. Each of the first, second, third detector units includes a first transistor and a second transistor connected in series. A gate of the second transistor is a floating gate. The peripheral circuit is on the peripheral region of the substrate and is coupled to the semiconductor detector. The multilayer interconnection structure is over the substrate. A first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector.

Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Abstract: A low voltage one-time-programmable memory includes a first conductive layer, a first via, a second conductive layer, a select transistor, a second via and a third conductive layer. The first via is electrically connected to the first conductive layer. The second conductive layer is electrically connected to the first via. The select transistor is electrically connected to the second conductive layer. The second via is electrically connected to the second conductive layer. The third conductive layer is electrically connected to the second via. A first current passed through the second via is a sum of a second current passed through the first via and a third current passed through the select transistor.

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Abstract: A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Abstract: A semiconductor device includes an insulating base layer, a semiconductor layer, an insulating layer, an isolation trench and a gettering site. The semiconductor layer and the insulating layer are disposed on the insulating base layer in sequence, and the isolation trench is disposed in the semiconductor layer and passes through the insulating layer. The isolation trench includes a first cross-section, a second cross-section and a third cross-section from top to bottom. The first cross-section is higher than the bottom surface of the insulating layer, and the second cross-section and the third cross-section are lower than the bottom surface of the insulating layer. The gettering site is disposed in the semiconductor layer and in contact with the isolation trench, and the vertex of the gettering site is lower than the second cross-section.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.