Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate.

Abstract: A probeless parallel test system for an integrated circuit (IC) includes an IC chip, a wireless power receiving module and a Build-In Self-Test (BIST) circuit. The wireless power receiving module is electrically connected to the IC chip. The BIST circuit is electrically connected to the wireless power receiving module and the IC chip. The wireless power receiving module, the BIST circuit and the IC chip are all formed on a wafer. The wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip. When receiving the electric power, the IC chip executes a functional operation, and transmits an operation result to the BIST circuit for testing.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack positioned over the semiconductor substrate. The semiconductor device structure includes a first doped structure and a second doped structure positioned at two opposite sides of the first gate stack and embedded in the semiconductor substrate. The semiconductor device structure includes a second gate stack positioned over the semiconductor substrate and adjacent to the second doped structure. The semiconductor device structure includes a third gate stack positioned over the semiconductor substrate. The semiconductor device structure includes an isolation structure embedded in the semiconductor substrate and between the second gate stack and the third gate stack. The isolation structure is wider and thinner than the second doped structure, and the isolation structure is made of an epitaxial material.

Abstract: A non-volatile memory includes a substrate, a fin structure, a gate structure, a transition layer, and a metal layer. The fin structure is protruded from the substrate. A first source/drain region and a second source/drain region are formed in the fin structure. The gate structure covers a top surface and two lateral surfaces of a part of the fin structure. The gate structure is arranged between the first source/drain region and the second source/drain region. The transition layer is in contact with the second source/drain region. The metal layer is in contact with the transition layer. By setting or resetting the transition layer, a resistance value of the transition layer is correspondingly changed.

Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.

Abstract: A cell structure of a non-volatile memory is provided. The cell structure includes a first metal layer, a first dielectric layer, a first material layer, a second material layer, a first transition layer, a second metal layer, a second dielectric layer, a third material layer, a fourth material layer, a second transition layer, and a third metal layer. The first dielectric layer has a first via, and the first metal layer is exposed through the first via. The first material layer and the second material layer are reacted with each other to form the first transition layer. The second dielectric layer has a second via, and the second metal layer is exposed through the second via. The third material layer and the fourth material layer are reacted with each other to form the second transition layer.

Abstract: A non-volatile memory includes a substrate, a fin structure, a gate structure, a transition layer, and a metal layer. The fin structure is protruded from the substrate. A first source/drain region and a second source/drain region are formed in the fin structure. The gate structure covers a top surface and two lateral surfaces of a part of the fin structure. The gate structure is arranged between the first source/drain region and the second source/drain region. The transition layer is in contact with the second source/drain region. The metal layer is in contact with the transition layer. By setting or resetting the transition layer, a resistance value of the transition layer is correspondingly changed.

Abstract: A three-dimensional integrated circuit includes a plurality of perpendicular stacked chips. Each chip of the plurality of perpendicular stacked chips includes at least one transistor, a sensing coil, and a magnetic sensor, wherein the magnetic sensor is installed above the at least one transistor and the sensing coil and the sensing coil is installed between the magnetic sensor and the at least one transistor. The chip utilizes the sensing coil to generate a magnetic field including data, and a first chip of the plurality of perpendicular stacked chips adjacent to the chip utilizes a magnetic sensor of the first chip to receive the data generated by the sensing coil of the chip through the magnetic field generated by the sensing coil of the chip.

Abstract: A cell structure of a non-volatile memory is provided. The cell structure includes a first metal layer, a first dielectric layer, a first material layer, a second material layer, a first transition layer, a second metal layer, a second dielectric layer, a third material layer, a fourth material layer, a second transition layer, and a third metal layer. The first dielectric layer has a first via, and the first metal layer is exposed through the first via. The first material layer and the second material layer are reacted with each other to form the first transition layer. The second dielectric layer has a second via, and the second metal layer is exposed through the second via. The third material layer and the fourth material layer are reacted with each other to form the second transition layer.

Abstract: A cell structure of a non-volatile memory includes a first metal layer, a first dielectric layer, a first transition layer, a second metal layer, a second dielectric layer, a second transition layer, and a third metal layer. The first dielectric layer is disposed over the first metal layer, and has a first via. The first transition layer is arranged between the first via and the first metal layer. The second metal layer is formed within the first via and contacted with the first transition layer. The second dielectric layer is disposed over the second metal layer and the first dielectric layer, and has a second via. The second transition layer is arranged between the second via and the second metal layer. The third metal layer is formed within the second via and contacted with the second transition layer.

Abstract: A method for manufacturing a resistive element of a non-volatile memory includes the following steps. An insulation layer is formed on a conductive region. The insulation layer is etched to form a via in the insulation layer, wherein a bottom of the via is contacted with a top surface of the conductive region. A dielectric layer is formed on an inner wall and the bottom of the via. A barrier layer is formed on the dielectric layer. A metal layer is filled into the via. The dielectric layer and the barrier layer are reacted with each other to form a transition layer.

Abstract: A method for manufacturing a resistive element of a non-volatile memory includes the following steps. An insulation layer is formed on a conductive region. The insulation layer is etched to form a via in the insulation layer, wherein a bottom of the via is contacted with a top surface of the conductive region. A dielectric layer is formed on an inner wall and the bottom of the via. A barrier layer is formed on the dielectric layer. A metal layer is filled into the via. The dielectric layer and the barrier layer are reacted with each other to form a transition layer.

Abstract: A memory cell of a non-volatile memory includes a storage transistor and a resistive element. The storage transistor includes a gate structure, a first doped region and a second doped region. A first end of the resistive element is connected to the second doped region. The storage transistor is programmed to be at least in a first storing status or a second storing status. The resistive element is programmed to be at least in the first storing status or the second storing status. A control terminal of the memory cell is connected to the gate structure. A first terminal of the memory cell is connected to the first doped region. A second terminal of the memory cell is connected to a second end of the resistive element.

Abstract: A cell structure of a non-volatile memory includes a first metal layer, a first dielectric layer, a first transition layer, a second metal layer, a second dielectric layer, a second transition layer, and a third metal layer. The first dielectric layer is disposed over the first metal layer, and has a first via. The first transition layer is arranged between the first via and the first metal layer. The second metal layer is formed within the first via and contacted with the first transition layer. The second dielectric layer is disposed over the second metal layer and the first dielectric layer, and has a second via. The second transition layer is arranged between the second via and the second metal layer. The third metal layer is formed within the second via and contacted with the second transition layer.

Abstract: A control method for a nonvolatile memory device with a vertically stacked structure is provided. The nonvolatile memory device includes a substrate, a common source line formed on the substrate, and plural memory blocks disposed over the substrate. Each memory block includes a cell string connected between a bit line and the common source line. Firstly, a first memory block of the plural memory blocks is selected as an active memory block, and one of the remaining memory blocks is selected as a second memory block. Then, a ground voltage is provided to the bit line of the second memory block, and the cell string of the second memory block is conducted, so that the ground voltage is transmitted from the bit line to the common source line through the cell string.

Abstract: A three-dimensional integrated circuit includes a plurality of perpendicular stacked chips. Each chip of the plurality of perpendicular stacked chips includes at least one transistor, a sensing coil, and a magnetic sensor, wherein the magnetic sensor is installed above the at least one transistor and the sensing coil and the sensing coil is installed between the magnetic sensor and the at least one transistor. The chip utilizes the sensing coil to generate a magnetic field including data, and a first chip of the plurality of perpendicular stacked chips adjacent to the chip utilizes a magnetic sensor of the first chip to receive the data generated by the sensing coil of the chip through the magnetic field generated by the sensing coil of the chip.

Abstract: A transistor is provided. The transistor includes a substrate, a gate electrode formed on the substrate, and multiple floating gates formed on the substrate. A fixed distance is designed between the adjacent floating gates. Wherein, the substrate, the multiple floating gates, and the gate electrode are separated by a plurality of active regions.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate.

Abstract: A memory cell, a memory array and an operation method are disclosed herein. The memory cell includes a substrate with a first conductivity type, a first doped region with a second conductivity type, a second doped region with the second conductivity type, a first floating gate, a second floating gate and a word gate. The first and the second doped region are disposed in the substrate. The first floating gate is disposed on the substrate and electrically coupled to the first doped region. The second floating gate is disposed on the substrate and electrically coupled to the second doped region. The word line gate is disposed on the substrate and between the first and second doped region, wherein the word gate includes a first part extending over the first floating gate and a second part extending over the second floating gate.