Abstract: A test structure for evaluating plasma damage in thin gate oxides is formed with a single polysilicon floating gate EEPROM device on which an antenna structure delivers charge to a floating gate through a tunnel oxide. The floating gate extends beyond the MOSFET channel in one direction, passing over field oxide and terminating in a pad over a thin tunnel oxide window formed over an isolated n+ diffusion. The n+ diffusion is connected to a metal antenna structure which is exposed to a processing plasma. Charge accumulated on the antenna during plasma exposure causes a tunnel current to flow through the tunnel oxide, and charge to accumulate on the floating gate. A second extension of the polysilicon floating gate passes over a second field oxide region and terminates in a pad over a thicker oxide formed on a second isolated n+ diffusion. The second n+ diffusion forms the control gate of the EEPROM and is connected by wiring to a probe pad.

Abstract: A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion.

Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract: A method of manufacturing a on-chip temperature controller by co-implanting P-type and N-type ions into poly load resistors. The N and P type implant dose can be selected to create the desired cut-off temperature. First, a polysilicon layer 30 is formed on a first insulation layer 20. The polysilicon layer 30 is patterning to form a first poly-load resistor 30A and a second poly-load resistor 30B. The first and the second poly-load resistors are connected to a temperature sensor circuit 12. Both p-type and n-type impurity ions are implanted into the polysilicon layer 30. An insulating dielectric layer 40 is formed over the polysilicon layer 30 and the first insulating layer 20. The polysilicon layer is annealed. The contact openings 44 are formed through the ILD dielectric layer 40 exposing portions of the polysilicon layer 30. Contacts 50 to the polysilicon layer 30 thereby forming a first and second poly-load resistors which are used a temperature on-chip sensors.

Abstract: A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.

Abstract: A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.

Abstract: A new method is provided for the creation of a Shallow Trench Isolation region. A layer of pad oxide is deposited on the surface of a substrate; a layer of nitride is deposited over the layer of pad oxide. The layers of pad oxide and nitride are patterned and etched over the region where the STI is to be formed, a trench is etched in the silicon for the STI region. A layer of TEOS, that serves as a buffer spacer oxide, is deposited over the surface of the layer of nitride thereby including the inside of the created trench. The layer of TEOS is etched removing the TEOS from the surface of the nitride and from the bottom of the trench but leaving a layer of TEOS in place along the sidewalls of the trench. The bottom of the trench is next etched after which the TEOS spacer buffer is removed from the sidewalls of the trench. The sidewalls of the trench now have a non-linear profile.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxide layer. Pattern the blanket silicon oxide layer, the floating gate conductor layer and the substrate in a patterning process with a single floating gate electrode mask forming floating gate electrodes from the floating gate conductor layer and the silicon oxide layer; and simultaneously form trenches in the substrate adjacent to the floating gate electrode and aligned with the floating gate electrodes thereby patterning the active region in the substrate. Form a blanket dielectric layer on the device filling the trenches and planarized with the top surface of the floating gate electrodes. Form an interconductor dielectric layer over the device including the floating gate electrodes. Form a control gate conductor over the interconductor dielectric layer.

Abstract: A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

Abstract: A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

Abstract: A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.

Abstract: A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer.

Abstract: A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.

Abstract: This is a method of forming a vertical memory device on a semiconductor substrate. Start by forming an initial mask with a first array of parallel strips, with a first orientation, on the surface of a silicon oxide layer on a substrate. Then form another mask with transverse strips to form gate trench openings between the first array of strips and the transverse strips. Next, etch floating gate trenches in the substrate through the gate trench openings. Dope the walls of the trenches with a threshold implant and remove exposed portions of the mask. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Strip the remainder of the masks. Form a tunnel oxide layer on the trench surfaces and a floating gate electrode in the trench on the tunnel oxide layer. Above the source/drain regions, form source drain conductor lines in the substrate in a parallel array.