Abstract: The present disclosure provides a method for extracting and separating flavonoids from Lindera aggregata leaves. The method includes: mixing Lindera aggregata leaves with an adsorbent, conducting elution with a matrix solid-phase dispersion (MSPD) extraction method, followed by concentration to obtain a Lindera aggregata leaf extract; conducting primary separation and secondary separation on the Lindera aggregata leaf extract by high-speed counter-current liquid chromatography (HSCCC), to separate quercetin-3-O-?-D-arabinofuranoside, a mixture of quercetin-3-O-?-D-glucoside and quercetin-5-O-?-D-glucoside, quercetin-3-O-rhamnopyranoside, and kaempferol-7-O-?-L-rhamnopyranoside; where a second solvent system used in the secondary separation includes ethyl acetate, n-butanol, an addictive and water, and the addictive includes cyclodextrin.

Abstract: The present disclosure provides a method for extracting and separating flavonoids from Lindera aggregata leaves. The method includes: mixing Lindera aggregata leaves with an adsorbent, conducting elution with a matrix solid-phase dispersion (MSPD) extraction method, followed by concentration to obtain a Lindera aggregata leaf extract; conducting primary separation and secondary separation on the Lindera aggregata leaf extract by high-speed counter-current liquid chromatography (HSCCC), to separate quercetin-3-O-?-D-arabinofuranoside, a mixture of quercetin-3-O-?-D-glucoside and quercetin-5-O-?-D-glucoside, quercetin-3-O-rhamnopyranoside, and kaempferol-7-O-?-L-rhamnopyranoside; where a second solvent system used in the secondary separation includes ethyl acetate, n-butanol, an addictive and water, and the addictive includes cyclodextrin.

Abstract: A data visualization method is disclosed, including receiving business data and classifying the business data according to a business type associated with the business data so as to form multiple sets of target data, processing at least one set of the multiple sets of target data to obtain update data for an interactive interface, the interactive interface corresponding to the business type of the at least one set of target data and configured to display the at least one set of target data; rendering the interactive interface based on the update data to update content of the interactive interface. Thereby, isolation of data of different business types and linkage of data of the same business type are achieved, which improves the efficiency of visualized presentation of data.

Abstract: Park monitoring methods, park monitoring systems, and computer-readable storage media are provided. A method includes: determining a first path from a current position of a first object to a first position; generating a 3D virtual image of a surrounding environment when the first object is moving along the first path based on a perspective of the first object; and when the first object is located at the first position, displaying a real image of the first position.

Abstract: The present application provides an antibody, such as a monoclonal antibody (mAb), or an antigen binding fragment thereof, that specifically recognizes TIGIT. Also provided are pharmaceutical compositions, or methods of making and using the antibody or antigen-binding fragment thereof.

Abstract: An ink container for photo-curable ink is disclosed, comprising a plurality of walls, the walls forming a closed space to be filled with UV photo-curable ink; the walls are non-transparent filter plates, but have light transmittance property, in a color scheme of yellow or orange, i.e., hue number of 3-8 in the PCCS hue circle, able to shield off the UV, the light transmittance property of the walls allows observing liquid level inside the ink container after filling with the UV photo-curable ink.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A method for processing a photomask for semiconductor devices. The method includes providing a partially completed mask structure, which has a backside and a face. The face includes a substrate material, a light blocking layer overlying the substrate material, and an overlying patterned photoresist layer overlying the light blocking layer. The method includes supporting the backside of the mask structure to maintain the mask structure in place and maintaining the face of the patterned photoresist layer in a direction parallel to a gravitational force and toward the gravitational force. The method includes rotating the mask structure in an annular manner as the patterned photoresist layer of the mask structure is being maintained in the direction parallel to the gravitational force and toward the gravitational force.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: According to an embodiment of the present invention, a lens module is provided, which includes a first lens assembly including a first patterned substrate, a first recess formed from a first surface of the first patterned substrate, a first lens element disposed in the first recess, and a second lens element disposed on the first patterned substrate, wherein the second lens element aligns along an optical axis through the first lens element.

Abstract: A semiconductor structure includes a first high-voltage well (HVW) region of a first conductivity type overlying a substrate, a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region, and a third HVW region of the second conductivity type underlying the second HVW region. A region underlying the first HVW region is substantially free from the third HVW region, wherein the third HVW region has a bottom lower than a bottom of the first HVW region. The semiconductor structure further includes an insulation region in a portion and extending from a top surface of the first HVW region into the first HVW region, a gate dielectric extending from over the first HVW region to over the second HVW region wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.