Patents by Inventor Chu-Feng Chen

Chu-Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210028309
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 28, 2021
    Inventors: Chu Fu CHEN, Chi-Feng HUANG, Chia-Chung CHEN, Chin-Lung CHEN, Victor Chiang LIANG, Chia-Cheng PAO
  • Patent number: 10868115
    Abstract: A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.
    Type: Grant
    Filed: June 22, 2019
    Date of Patent: December 15, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10784781
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
  • Patent number: 10680059
    Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: June 9, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10629726
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 10622473
    Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.
    Type: Grant
    Filed: August 19, 2018
    Date of Patent: April 14, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen, YU-Ting Yeh
  • Patent number: 10622440
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 14, 2020
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Publication number: 20200111906
    Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semiconductor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.
    Type: Application
    Filed: August 13, 2019
    Publication date: April 9, 2020
    Inventors: Tsung-Yi Huang, Kun-Huang Yu, Ying-Shiou Lin, Chu-Feng Chen, Chung-Yu Hung, Yi-Rong Tu
  • Patent number: 10596171
    Abstract: Provided is a compound of Formula (I) below, or a pharmaceutically acceptable salt, metabolite, or prodrug thereof: wherein: A1 is CR4 or N; A2 is CR5R6 or NR7; A3 is CR5?R6? or NR7?; each of R1, R2, R2?, R3, R3?, R4, R5, R5?, R6, R6?, R7, and R7?, independently, is hydrogen, deuterium, halogen, cyano, hydroxyl, carboxyl, amino, formyl, nitro, C1-6 alkyl, C2-6 alkenyl, C2-6 alkynyl, C1-6 alkoxy, C2-6 alkenyloxy, C1-6 alkylcarbonyl, C1-6 alkyloxycarbonyl, C1-6 alkylamine, C3-20 carbocyclyl, or C3-20 heterocyclyl; or R5 and R6, R5? and R6?, or R5 and R5?, together with the adjacent atom to which they are each attached, form C3-10 carbocyclyl or C3-10 heterocyclyl. Further provided are a method of using the above-described compound, or the pharmaceutically acceptable salt, metabolite, or prodrug thereof for treating influenza and a pharmaceutical composition containing same.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 24, 2020
    Assignee: TaiGen Biotechnology Co., Ltd.
    Inventors: Chu-Chung Lin, Hung-Chuan Chen, Chiayn Chiang, Chi-Feng Yen, Ming-Chu Hsu
  • Publication number: 20200044022
    Abstract: A high voltage device includes: a semiconductor layer, an isolation region, a deep well, a buried layer, a first high voltage well, a first conductivity type well, a second high voltage well, a body region, a body contact, a deep well column, a gate, a source and a drain. The deep well column is located between the drain and a boundary of the conductive layer which is near the source in a channel direction. The deep well column is a minority carriers absorption channel, to avoid turning ON a parasitic transistor in the high voltage device.
    Type: Application
    Filed: June 22, 2019
    Publication date: February 6, 2020
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Publication number: 20190224198
    Abstract: Provided is a compound of Formula (I) below, or a pharmaceutically acceptable salt, metabolite, or prodrug thereof: wherein: A1 is CR4 or N; A2 is CR5R6 or NR7; A3 is CR5?R6? or NR7?; each of R1, R2, R2?, R3, R3?, R4, R5, R5?, R6, R6?, R7, and R7?, independently, is hydrogen, deuterium, halogen, cyano, hydroxyl, carboxyl, amino, formyl, nitro, C1-6 alkyl, C2-6 alkenyl, C2-6 alkynyl, C1-6 alkoxy, C2-6 alkenyloxy, C1-6 alkylcarbonyl, C1-6 alkyloxycarbonyl, C1-6 alkylamine, C3-20 carbocyclyl, or C3-20 heterocyclyl; or R5 and R6, R5? and R6?, or R5 and R5?, together with the adjacent atom to which they are each attached, form C3-10 carbocyclyl or C3-10 heterocyclyl. Further provided are a method of using the above-described compound, or the pharmaceutically acceptable salt, metabolite, or prodrug thereof for treating influenza and a pharmaceutical composition containing same.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 25, 2019
    Inventors: Chu-Chung Lin, Hung-Chuan Chen, Chiayn Chiang, Chi-Feng Yen, Ming-Chu Hsu
  • Publication number: 20190165678
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 30, 2019
    Inventors: Chu Fu CHEN, Chi-Feng HUANG, Chia-Chung CHEN, Chin-Lung CHEN, Victor Chiang LIANG, Chia-Cheng PAO
  • Publication number: 20190131390
    Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 2, 2019
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Publication number: 20190115468
    Abstract: A high voltage MOS device includes: a well, a body region, a gate, a source, plural body contact regions and a drain. The plural body contact regions are formed in the body region, wherein each of the body contact region is located beneath the top surface and contacts the top surface in the vertical direction, and is in contact or not in contact with the gate in the lateral direction. The plural body contact regions are arranged substantially in parallel in the width direction and any two neighboring body contact regions are not in contact with each other in the width direction. The gate includes a poly-silicon layer which serves as the only electrical contact of the gate, and every part of the poly-silicon layer is the first conductivity type.
    Type: Application
    Filed: August 19, 2018
    Publication date: April 18, 2019
    Inventors: Tsung-Yi Huang, Chu-Feng Chen, Yu-Ting Yeh
  • Publication number: 20190096992
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10236375
    Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: March 19, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 10177220
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: January 8, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Publication number: 20180350903
    Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.
    Type: Application
    Filed: July 27, 2017
    Publication date: December 6, 2018
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Publication number: 20180331211
    Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.
    Type: Application
    Filed: February 5, 2018
    Publication date: November 15, 2018
    Inventors: Tsung-Yi Huang, Chu-Feng Chen
  • Patent number: 9853099
    Abstract: The present invention provides a DMOS device and a manufacturing method thereof. The DMOS device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, a drift buried region and a buried region. A first PN junction is formed between the high voltage well and an upper surface of the substrate. From a cross-section view, along the channel direction, a second PN junction is formed between the drift buried region and the buried region or formed between the high voltage well and the buried region. Along the channel direction, the first PN junction and the second PN junction have respective depths. The depth is defined as a distance extending from the upper face of the epitaxial layer downward along a vertical direction. The depth of the second PN junction is shallower than the depth of the first PN junction.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 26, 2017
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Chu-Feng Chen