Patents by Inventor Chu-Feng Chen
Chu-Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9853099Abstract: The present invention provides a DMOS device and a manufacturing method thereof. The DMOS device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, a drift buried region and a buried region. A first PN junction is formed between the high voltage well and an upper surface of the substrate. From a cross-section view, along the channel direction, a second PN junction is formed between the drift buried region and the buried region or formed between the high voltage well and the buried region. Along the channel direction, the first PN junction and the second PN junction have respective depths. The depth is defined as a distance extending from the upper face of the epitaxial layer downward along a vertical direction. The depth of the second PN junction is shallower than the depth of the first PN junction.Type: GrantFiled: April 18, 2017Date of Patent: December 26, 2017Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Tsung-Yi Huang, Chu-Feng Chen
-
Patent number: 9831305Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.Type: GrantFiled: May 6, 2016Date of Patent: November 28, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chu-Feng Chen, Wei-Chun Chou, Chien-Wei Chiu
-
Publication number: 20170323938Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.Type: ApplicationFiled: May 6, 2016Publication date: November 9, 2017Applicant: Vanguard International Semiconductor CorporationInventors: Chu-Feng CHEN, Wei-Chun CHOU, Chien-Wei CHIU
-
Publication number: 20160172490Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Applicant: Vanguard International Semiconductor CorporationInventors: Chung-Ren LAO, Hsing-Chao LIU, Chu-Feng CHEN, Wei-Chun CHOU
-
Patent number: 9343572Abstract: A high-voltage semiconductor device is provided. The high-voltage semiconductor device includes a substrate; an epitaxial layer and a gate structure; a first conductive type first high-voltage well region and a second conductive type high-voltage well region disposed in the epitaxial layer at opposite sides of the gate structure respectively, wherein the first conductive type is different from the second conductive type; a source region and a drain region; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. A method for manufacturing the high-voltage semiconductor device is also provided.Type: GrantFiled: January 23, 2015Date of Patent: May 17, 2016Assignee: Vangaurd International Semiconductor CorporationInventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
-
Patent number: 9224862Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.Type: GrantFiled: August 26, 2014Date of Patent: December 29, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
-
Publication number: 20150054071Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.Type: ApplicationFiled: August 26, 2014Publication date: February 26, 2015Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
-
Patent number: 8847332Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.Type: GrantFiled: April 20, 2011Date of Patent: September 30, 2014Assignee: Vanguard International Semiconductor CorporationInventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
-
Patent number: 8466019Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.Type: GrantFiled: October 6, 2011Date of Patent: June 18, 2013Assignee: Vanguard International Semiconductor CorporationInventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
-
Publication number: 20120267715Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
-
Publication number: 20120025308Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.Type: ApplicationFiled: October 6, 2011Publication date: February 2, 2012Applicant: VANGUARD INTERNATIONAL SEMICONDUCTORInventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
-
Patent number: 8058121Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.Type: GrantFiled: June 29, 2009Date of Patent: November 15, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chu-Feng Chen, Chung-Ren Lao, Pai-Chun Kuo, Chien-Hsien Song, Hua-Chun Chiue, An-Hung Lin
-
Publication number: 20090321825Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.Type: ApplicationFiled: June 29, 2009Publication date: December 31, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chu-Feng CHEN, Chung-Ren LAO, Pai-Chun KUO, Chien-Hsien SONG, Hua-Chun CHIUE, An-Hung LIN