Abstract: A digital to analog converter for fiber optic gyroscope is disclosed. The digital to analog converter for fiber optic gyroscope includes a random unit generating a random number signal, a plurality of encoding units coupled with the random unit, a plurality of control units respectively one to one coupled with the plurality of encoding units, a current source array coupled with the plurality of control units, and an output load electrically connected to the current source array. Each of the plurality of encoding units converts a plurality of digital signals to a plurality of spin signals according to the random number signal. Each of the plurality of control units converts the plurality of spin signals to a plurality of logic signals. The current source array generates a total current according to the plurality of logic signals. The total current passes through the output load and forms an analog signal.

Abstract: A DC-DC buck converter includes a buck conversion circuit, a PWM control circuit and a light-load control circuit. A switching circuit in the buck conversion circuit includes multiple upper switching elements and lower switching elements. The PWM control circuit is coupled to the buck conversion circuit and output a control signal to control the upper and lower switching elements. The light-load control circuit, coupled to the PWM control circuit and the buck conversion circuit for receiving an output voltage, the control signal and a light-load threshold value. The light-load control circuit is provided to determine whether the DC-DC buck converter is in a light load state and turn off at least one of the upper switching elements and at least one of the lower switching elements in the light load state.

Abstract: A DC-DC buck converter includes a buck conversion circuit, a PWM control circuit and a light-load control circuit. A switching circuit in the buck conversion circuit includes multiple upper switching elements and lower switching elements. The PWM control circuit is coupled to the buck conversion circuit and output a control signal to control the upper and lower switching elements. The light-load control circuit, coupled to the PWM control circuit and the buck conversion circuit for receiving an output voltage, the control signal and a light-load threshold value. The light-load control circuit is provided to determine whether the DC-DC buck converter is in a light load state and turn off at least one of the upper switching elements and at least one of the lower switching elements in the light load state.

Abstract: A peak detector utilizes two choppers to cancel offset voltage of a transconductance amplifier, so the influence of the offset voltage is preventable and the peak detection accuracy of the peak detector can be improved significantly.

Abstract: A phase shift detector comprises a comparator for detecting phase information of a signal and an offset calibration circuit. In order to prevent input offset voltage of the comparator from affecting phase detection accuracy, bulk voltage is inputted to the comparator from the offset calibration circuit to adjust threshold voltage of transistor in the comparator for compensating input offset voltage of the comparator and improving accuracy of the phase shift detector.

Abstract: Estimation circuit for SOC and SOH of battery includes a control circuit, a current estimation circuit, an open-circuit voltage detection circuit, an optional multiplexer and an electrical-capacity calculation circuit. The control circuit operates under six modes based on a reset signal, a voltage signal and a current signal. The current estimation circuit comprises a current modification circuit and a Coulomb integral circuit, the current modification circuit receives the current signal and outputs a modifying current signal, the Coulomb integral circuit integrates the modifying current signal to obtain an estimating electrical-capacity value. The open-circuit voltage detection circuit receives the voltage signal and outputs an initial electrical-capacity value. The optional multiplexer receives an estimation optional signal, the estimating electrical-capacity value and the initial electrical-capacity value to output an estimating electrical-capacity signal.

Abstract: Estimation circuit for SOC and SOH of battery includes a control circuit, a current estimation circuit, an open-circuit voltage detection circuit, an optional multiplexer and an electrical-capacity calculation circuit. The control circuit operates under six modes based on a reset signal, a voltage signal and a current signal. The current estimation circuit comprises a current modification circuit and a Coulomb integral circuit, the current modification circuit receives the current signal and outputs a modifying current signal, the Coulomb integral circuit integrates the modifying current signal to obtain an estimating electrical-capacity value. The open-circuit voltage detection circuit receives the voltage signal and outputs an initial electrical-capacity value. The optional multiplexer receives an estimation optional signal, the estimating electrical-capacity value and the initial electrical-capacity value to output an estimating electrical-capacity signal.

Abstract: A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.

Abstract: A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.

Abstract: The present invention relates to a low dropout regulator, and more particularly to a low dropout regulator without load capacitor and ESR (equivalent series resistance) designed in response to the discharge curve of a Li-ion battery, includes an input terminal, a reference circuit, a power transfer element, a level regulating device, a regulating circuit, and a first N-type MOSFET. The regulating circuit detects a load change at an output terminal, amplifies the load change, and couples it to the level regulating device. The level regulating device receives and boosts a received signal and transmits the received signal to the power transfer element, so as to achieve the effect of controlling the power of a power supply.

Abstract: A portable detection system for allergic diseases includes a filtration-based inspection module and a reader module. The filtration-based inspection module includes an FPW sensor and a liquid sample filtration apparatus, wherein the liquid sample filtration apparatus includes an injection opening, a passage module, a filtering membrane and a gathering aperture. The injection opening is in communication with the gathering aperture. The FPW sensor comprises a frame body, a carrier and a sensing chip having an accommodating slot in communication with the gathering aperture. The carrier comprises a plurality of conductive terminals, and the conductive terminals are electrically connected with the sensing chip. The reader module comprises a connection slot capable of being inserted by the conductive terminals of the carrier.

Abstract: A portable detection system for allergic diseases includes a filtration-based inspection module and a reader module. The filtration-based inspection module includes an FPW sensor and a liquid sample filtration apparatus, wherein the liquid sample filtration apparatus includes an injection opening, a passage module, a filtering membrane and a gathering aperture. The injection opening is in communication with the gathering aperture. The FPW sensor comprises a frame body, a carrier and a sensing chip having an accommodating slot in communication with the gathering aperture. The carrier comprises a plurality of conductive terminals, and the conductive terminals are electrically connected with the sensing chip. The reader module comprises a connection slot capable of being inserted by the conductive terminals of the carrier.

Abstract: A frequency shift detector includes a digital control unit, a digital/analog converter, a reagent concentration detecting circuit and a frequency difference generator, wherein the digital control unit includes a control circuit and a direct digital frequency synthesizer electrically connected with the control circuit, and the control circuit comprises a reset terminal and a pulse input terminal. The digital control unit proceeds with accurate concentration detection for various samples borne on the reagent concentration detecting circuit.

Abstract: An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.

Abstract: An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.

Abstract: An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.

Abstract: A charging circuit integrated into a chip, comprising a charging unit, a switch unit, a biasing unit, a voltage-dividing unit, and a comparing unit. The charging unit is connected between a power supply input and a load for outputting a constant current based on a constant bias voltage supplied by the power supply input in order to charge the load. The switch unit is connected between the charging unit and the power supply input for turning on or cutting off the charging unit. The voltage-dividing unit generates a first signal to the comparing unit according to a voltage of the load. The biasing unit outputs a second signal having a constant voltage to the comparing unit. The comparing unit compares the first signal with the second signal for cutting off or turning on the switch unit, bringing the charging unit to charge or stop charging the load, respectively.

Abstract: A threshold voltage detection circuit comprises a first inverter, a first transistor, a second transistor, a third transistor and a fourth transistor. The first inverter comprises a first terminal and a second terminal, a first electrode of the first transistor is electrically connected with the second terminal of the first inverter, a fourth electrode of the second transistor is electrically connected with the first terminal of the first inverter, a seventh electrode of the third transistor is electrically connected with the second terminal of the first inverter and the first electrode of the first transistor, a tenth electrode of the fourth transistor is electrically connected with a third electrode of the first transistor and a fifth electrode of the second transistor, and an eleventh electrode of the fourth transistor is electrically connected with a ninth electrode of the third transistor.

Abstract: A threshold voltage detection circuit comprises a first inverter, a first transistor, a second transistor, a third transistor and a fourth transistor. The first inverter comprises a first terminal and a second terminal, a first electrode of the first transistor is electrically connected with the second terminal of the first inverter, a fourth electrode of the second transistor is electrically connected with the first terminal of the first inverter, a seventh electrode of the third transistor is electrically connected with the second terminal of the first inverter and the first electrode of the first transistor, a tenth electrode of the fourth transistor is electrically connected with a third electrode of the first transistor and a fifth electrode of the second transistor, and an eleventh electrode of the fourth transistor is electrically connected with a ninth electrode of the third transistor.

Abstract: The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.