Patents by Inventor Chua Swee Kwang
Chua Swee Kwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811278Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: June 7, 2019Date of Patent: October 20, 2020Assignee: Micron Technology, Inc.Inventors: Chia Y. Poo, Low Siu Waf, Boon Suan Jeung, Eng M. Koon, Chua Swee Kwang
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Publication number: 20190362988Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: ApplicationFiled: June 7, 2019Publication date: November 28, 2019Inventors: Chia Y. Poo, Low Siu Waf, Boon Suan Jeung, Eng M. Koon, Chua Swee Kwang
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Patent number: 10453704Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: October 31, 2016Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventors: Chia Y. Poo, Low Siu Waf, Boon Suan Jeung, Eng M. Koon, Chua Swee Kwang
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Patent number: 10431531Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.Type: GrantFiled: August 8, 2018Date of Patent: October 1, 2019Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Yong Poo Chia
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Publication number: 20180350730Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.Type: ApplicationFiled: August 8, 2018Publication date: December 6, 2018Inventors: Chua Swee Kwang, Yong Poo Chia
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Patent number: 10074599Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.Type: GrantFiled: June 12, 2017Date of Patent: September 11, 2018Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Yong Poo Chia
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Publication number: 20170278775Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Inventors: Chua Swee Kwang, Yong Poo Chia
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Patent number: 9679834Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.Type: GrantFiled: January 19, 2016Date of Patent: June 13, 2017Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Yong Poo Chia
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Publication number: 20160247749Abstract: Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle.Type: ApplicationFiled: January 19, 2016Publication date: August 25, 2016Inventors: Chua Swee Kwang, Yong Poo Chia
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Patent number: 8174105Abstract: A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess, and a discrete component contained in the recess encapsulated in a die attach polymer. The stacked semiconductor package also includes interconnects electrically connecting the semiconductor dice and discrete components, and an encapsulant encapsulating the dice and the interconnects.Type: GrantFiled: May 18, 2011Date of Patent: May 8, 2012Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Chia Yong Poo
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Patent number: 8138617Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.Type: GrantFiled: August 30, 2004Date of Patent: March 20, 2012Assignee: Round Rock Research, LLCInventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Eng Meow Koon, Ser Bok Leng, Chua Swee Kwang, So Chee Chung, Ho Kwok Seng
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Publication number: 20110215438Abstract: A stacked semiconductor package includes a substrate and a plurality of semiconductor dice stacked on the substrate. Each semiconductor die includes a recess, and a discrete component contained in the recess encapsulated in a die attach polymer. The stacked semiconductor package also includes interconnects electrically connecting the semiconductor dice and discrete components, and an encapsulant encapsulating the dice and the interconnects.Type: ApplicationFiled: May 18, 2011Publication date: September 8, 2011Inventors: Chua Swee Kwang, Chia Yong Poo
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Patent number: 8008126Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.Type: GrantFiled: November 24, 2009Date of Patent: August 30, 2011Assignee: Micron Technology, Inc.Inventors: Boon Suan Jeung, Chia Yong Poo, Low Siu Waf, Eng Meow Koon, Chua Swee Kwang, Huang Shuang Wu, Neo Yong Loo, Zhou Wei
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Publication number: 20110175206Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Chua Swee Kwang, Boon Suan Jeung, Chia Yong Poo
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Patent number: 7964946Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.Type: GrantFiled: August 26, 2010Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Chia Yong Poo
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Publication number: 20110012253Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.Type: ApplicationFiled: August 26, 2010Publication date: January 20, 2011Inventors: Chua Swee Kwang, Chia Yong Poo
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Patent number: 7807502Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.Type: GrantFiled: April 19, 2010Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Chia Yong Poo
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Publication number: 20100203677Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.Type: ApplicationFiled: April 19, 2010Publication date: August 12, 2010Inventors: Chua Swee Kwang, Chia Yong Poo
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Publication number: 20100133662Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.Type: ApplicationFiled: January 29, 2010Publication date: June 3, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Chua Swee Kwang, Boon Suan Jeung, Chia Yong Poo
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Patent number: 7723831Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.Type: GrantFiled: June 25, 2007Date of Patent: May 25, 2010Assignee: Micron Technology, Inc.Inventors: Chua Swee Kwang, Chia Yong Poo