Abstract: A driving structure between front and rear wheels has two gear disks with wheel hub sleeves, pushing rolls and axle cores are inserted at the centers of the gear disks. Arresting members with polygonal crown supporting ribs on the circumferences are mounted between the axle cores and the pushing rolls to form wheel hubs disposed on the turning axles of the front and the rear wheels of the mobiles such as the bicycle and beach mobile. Two bevel gears are engaged with the gear disks and are connected by a steel cable so as to synchronously device the front and rear wheels.

Abstract: A folding structure of scooter mainly comprises of a front and a rear footboards and a hollow sleeve panel engaged with the front and the rear footboards, wherein the sliding grooves in the shapes of long holes are situated respectively on the side edges of the front and the rear footboards; the through holes disposed respectively on the four corners of the sleeve panel at responding positions to the sliding grooves of the front and the rear footboards for sleeving the front and the rear footboards into the sleeve panel and then insert the bolts to screw the through holes on the sleeve panel and the sliding grooves on the front and the rear footboards to make the front and the rear footboards expandable to be pulled outwards for the user to step on to slide and contractable inside the sleeve panel to reduce the volume for facilitating carriage, shipping and storage.

Abstract: A process for fabricating a lower electrode of a capacitor on a substrate having a dielectric layer formed thereon. A node contact opening is first formed in the dielectric layer to expose a part of a conductive portion on the substrate. A node contact is then formed in the node contact opening such that the node contact protrudes from the dielectric layer. Subsequently, an insulating layer and a conductive layer are formed in sequence on the dielectric layer and the node contacts. The conductive layer and the insulating layer are patterned in sequence to expose a part of the node contacts and leave the residual insulating layer as a protruding part and a link layer, in which the protruding part is located on a part of the node contacts and a part of the dielectric layer, and the link layer is located on the dielectric layer outside the node contacts, serving as a link for the dielectric layer and the protruding part.

Abstract: A method of fabricating a capacitor includes formation of a stacked layer formed by alternately forming conductive layers and isolation layers and then patterning these layers to form a stacked layer. An opening is formed above the source/drain region. A conductive spacer is formed on the sidewall of the opening. The conductive spacer is used as a mask. The dielectric layer below the stacked layer exposed by the opening is removed to form a contact hole. The top isolation layer of the stacked layer is removed. A conductive layer is formed over the substrate to fill the contact hole. The conductive spacer is covered by the conductive layer to form a raised region. A stacked spacer is formed beside the raised region. The isolation spacers of the stacked spacer and the isolation layer are removed to expose a storage electrode.

Abstract: An improved torsion shock absorber has a curved clevis rocker arm and a solid rocker arm. Mounting holes are formed through one rounded end each of the rocker arms and bush holes through opposite rounded ends, each having symmetrical notches respectively machined along the inner circumferences. A torsion shaft of a spring steel is inserted into the bush holes of the rocker arms, and into the holes of corresponding mounting rings and a torque seat, a faced washer and a bushing are placed in the bush hole opening of the solid rocker arm, and a C-shaped circlip is fitted into each of the two ends of the torsion shaft. The mounting holes of the clevis rocker arm and the solid rocker arm are then attached to different force receiving entities.

Abstract: A method is disclosed for forming the lower storage node and contact for capacitors on a semiconductor wafer. The method includes an etch back process to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer. When a contact plug is formed during a subsequent deposition process, the rounded shoulder results in local enlargement of the contact plug as well as filleting of reentrant corners. The contact plug therefore sustains substantially reduced mechanical stress during subsequent wafer cleaning processes. This stress reduction results in a reduced rate of lower node collapse and increased production yield of finished product.

Abstract: A method for forming a capacitor in DRAM is disclosed. The method includes: providing a conductor defined on a first dielectric layer; forming a second dielectric layer on the conductor; then forming a polysilicon layer on the second dielectric layer, the polysilicon layer serves as an etching mask; next, etching the second dielectric layer; removing said polysilicon layer; etching said conductor; and finally removing said second dielectric layer.

Abstract: A CPU heat sink includes a copper bottom panel, a plurality of copper radiating fins arranged in parallel on the bottom panel, the radiating fins each having a transverse foot bar, a plurality of strips respectively upwardly extended from the transverse foot bar and arranged in parallel, and a plurality of horizontal locating flanges respectively extended from the transverse foot bar at right angles, and an aluminum base molded on the bottom panel and the transverse foot bar and locating flanges of each radiating fin by die casting, the aluminum base having four upright posts disposed in four corners, the upright posts each having a square top and a screw hole on the square top, and four bearing blocks respectively fastened to the upright posts of the aluminum base and adapted to support a fan above the radiating fins, the bearing blocks each having a countersunk hole fastened to the screw hole of one upright post of the aluminum base by a screw, and at least one screw hole for the mounting of a fan.

Abstract: An antishock structure of scooter featuring a U-shaped anchor plate having symmetrical anchor holes disposed on top and bottom of its front and back surfaces; after the lower anchor holes are connected to wheel axles respectively, the other end of wheel axles is jointed with a front wheel respectively. A lug is arranged at the upper margin of the end of each wheel axle that enables the ends of two antishock members to be connected to the upper anchor hole of said anchor plate and the lug of said wheel axle respectively. As such, when the scooter is moving, the two antishock members provide a cushioning effect.

Abstract: A silicon oxide layer is formed on a substrate surface of a semiconductor wafer. A node contact is formed in the silicon oxide layer. A storage node is formed on the silicon oxide layer and connects to the node contact. An ion implantation process is performed as a surface process on the silicon oxide layer. A silicon nitride layer is subsequently formed on the surfaces of the silicon oxide layer and the storage node. Finally, a high-temperature oxidation process is performed. The surface process reduces the difference in the incubation time for the silicon nitride layer deposited on the silicon oxide layer and on the surface of the storage node. The surface process also relieves problems associated with the nonuniformity in thickness of the silicon nitride layer. Neck-oxidation at the interface of the storage node and the node contact is thus prevented.

Abstract: An improved structure scooter capable of responsive and stable, time- and energy-saving, as well as safe and convenient operation and utilization that is comprised of a footboard, a front wheel assembly, and a rear wheel assembly. The front wheel assembly is disposed at the anterior aspect of the footboard and is equipped at the center with an extension plate of a front mounting block—the extension plate providing for assembly to the footboard, a topside stem having a handhold at its upper extent and an active sleeve, and a front mounting block having a support fixture installed on its two sides. Installed to through-holes in the outer sides of the support fixtures are movable side connecting rods and situated at their lower ends are the mounting holes of axles stays that provides for the installation of front wheels. Situated at the upper ends of the left and right side connecting rods is a top connecting rod that provides for the synchronous deflection of the side connecting rods.

Abstract: A fabrication method for a borderless buried bit line is described. A substrate wherein a plurality of word lines and source/drain regions formed thereon is provided. A first insulation material is formed over the substrate and a node landing pad is formed in the first insulation material, wherein the node landing pad is covered by a second insulation material. A bit line contact is further formed in the first insulation material, wherein the bit line contact is covered by a third insulation material. Therefore, a trench is further formed along the sides of the bit line contact, traversing across the first insulation material. A partial filling of the trench with a conductive material, followed by filling the trench with a fourth insulation layer to complete the formation of the buried bit line.

Abstract: The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole.

Abstract: A method for forming a MOSFET is described. The feature of this invention is that an epitaxial silicon layer with device isolation structures is formed over a substrate, wherein each device isolation structure is made of oxide. The invention need not etch the substrate for forming a device isolation structure. As a result, the invention not only prevents stress and dislocation generation and avoids leakage current, but also provides an easily method for forming a device isolation structure.

Abstract: A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole.

Abstract: A method of forming a borderless contact is described. An ion implantation process and a thermal process are performed on a device isolation structure to form a silicon nitride layer therein. During a process of forming a borderless contact window, the silicon nitride layer can serve as an etching stop layer to protect the device isolation structure from overetching. As a result, no recess is formed, and leakage current is avoided.

Abstract: A method of fabricating a node contact hole is disclosed. The fabrication includes the steps as follows. At first, the first interpoly dielectric (IPD1) layer is formed over the semiconductor substrate. The landing pad is formed in the first interpoly dielectric layer. The polycide bit line is formed on the first interpoly dielectric layer. Afterwards, the second interpoly dielectric (IPD2) layer is formed over the first interpoly dielectric layer. Next, the defined photoresist layer is formed on the second interpoly dielectric layer, then using reflow and curing processes to form the heated photoresist layer. Afterwards, a portion of the second interpoly dielectric layer is firstly etched, using the heated photoresist layer as a mask. The depth is formed in the second interpoly dielectric layer. Then the heated photoresist layer is removed. Next, in order to the silicon nitride layer and the polysilicon layer are deposited over the second interpoly dielectric layer.

Abstract: A method of forming a capacitor for a dynamic random access memory (DRAM) cell using a selective hemispherical grain (s-HSG) structure after the removal of SiON by phosphoric acid (H3PO4) is disclosed. The method includes: Providing a semiconductor substrate having a semiconductor structure formed thereon; forming an interlayer dielectric layer over the semiconductor structure; patterning the interlayer dielectric layer; depositing an amorphous-silicon (a-Si) layer over the interlayer dielectric layer; depositing a SiON layer on the a-Si layer; patterning the SiON layer and the a-Si layer layer; removing the SiON layer by H3PO4 wet etching; forming a s-HSG silicon layer over the patterned a-Si layer; depositing a conformal interpoly dielectric layer along a surface of the resulting structure; and finally forming a polysilicon layer over the interpoly dielectric layer.

Abstract: A method of fabricating a bottom electrode for a capacitor is described in which a dielectric layer is formed on a substrate already comprising an isolation layer, an etching stop layer and a landing pad. Bit line structures and spacers are further formed on the dielectric layer. A node contact window opening is formed in the dielectric layer, exposing the landing pad, and a conformal first conductive layer is formed on the substrate. After a specially patterned mask layer is formed and the exposed first conductive layer is removed, an extended portion is formed connecting to the conductive layer to complete the fabrication of the columnar bottom electrode for a capacitor.