Patents by Inventor Chuan Wang

Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11962847
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 16, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chia-Hao Chang, You-Tsai Jeng, Kai-Wen Yeh, Yi-Cheng Chen, Te-Chuan Wang, Kai-Wen Cheng, Chin-Lung Lin, Tai-Lai Tung, Ko-Yin Lai
  • Patent number: 11961866
    Abstract: A method of forming an image sensor includes forming a photodiode within a semiconductor substrate. The method further includes disposing an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) over the photodiode; and a plurality of dielectric layers over the CESL, wherein at least one dielectric layer of the plurality of dielectric layers comprises a low dielectric constant (low-k) material. The method further includes patterning at least the plurality of dielectric layers, wherein patterning at least the plurality of dielectric layers comprises defining an opening above an active region of the photodiode. The method further includes depositing a cap layer on sidewalls of the opening, wherein the cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Chi Wang, Chia-Ping Lai, Chung-Chuan Tseng
  • Patent number: 11961763
    Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Chuan You, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240117451
    Abstract: Positive reference spiked in collected sample for use in qualitatively and quantitatively detecting viral RNA.
    Type: Application
    Filed: March 10, 2021
    Publication date: April 11, 2024
    Inventors: Shuwei YANG, Liancheng HUANG, Feifei FENG, Longwen SU, Kun LIN, Can TANG, Chen LIANG, Yuanmei WANG, Yanqing CAI, Yilin PANG, Chuan SHEN, Zhixue YU
  • Publication number: 20240117402
    Abstract: The present invention relates to methods that employ enzymes having Asx-specific ligase and cyclase activity, namely butelase-1, VyPAL2 and OaAEPI b, as a means for engineering novel (poly) peptide theranostics. The differential substrate specificities and differential optimal pH of the Asx-specific ligase and cyclase are used to provide sufficient orthogonality for a tandem ligation and cyclization of proteins. Also encompassed are the corresponding uses.
    Type: Application
    Filed: February 10, 2022
    Publication date: April 11, 2024
    Inventors: Chuan Fa Liu, Dingpeng Zhang, Zhen Wang, James P. Tam
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11955552
    Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Shih-Chuan Chiu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11953521
    Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 9, 2024
    Assignee: BAO HONG SEMI TECHNOLOGY CO., LTD.
    Inventors: Chao-Cheng Ting, Li-Hong Lu, Huai-Yi Wang, Lung-Chuan Tsai
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Publication number: 20240113142
    Abstract: An image sensor includes a group of sensor units, a color filter layer disposed within the group of sensor units, and a dielectric structure and a metasurface disposed corresponding to the color filter layer. The metasurface includes a plurality of peripheral nanoposts located at corners of the group of sensor units from top view, respectively, a central nanopost enclosed by the plurality of peripheral nanoposts, and a filling material laterally surrounding the plurality of peripheral nanoposts and the central nanopost. The central nanopost is offset from a center point of the group of sensor units by a distance from top view.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Po-Han FU, Wei-Ko WANG, Shih-Liang KU, Chin-Chuan HSIEH
  • Publication number: 20240113199
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.
    Type: Application
    Filed: February 7, 2023
    Publication date: April 4, 2024
    Inventors: Jia-Chuan YOU, Chia-Hao Chang, Kuo-Cheng Chiang, Chin-Hao Wang
  • Patent number: 11947879
    Abstract: An interactive information system includes: a first frame, a first interactive module arranged in the first frame, a second frame, a control module arranged in the second frame and configured to generate a graphic user interface (GUI) and to perform a function of the interactive information system based on the first user input; and a first internal cable connecting the first interactive module bridge board and the control module and configured to transmit the plurality of inter-frame signals between the first frame and the second frame. The first interactive module includes: a first display module for display of the GUI; a first touch input module configured to receive a first user input to the GUI; and a first interactive module bridge board configured to transmit a plurality of inter-frame signals comprising electrical signals of the first display module and the first touch input module.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: April 2, 2024
    Assignee: Flytech Technology Co., Ltd.
    Inventors: Tai-Seng Lam, Po-Hung Lin, Hsuan-Chuan Wang, Yong-Shun Kuan
  • Patent number: 11949175
    Abstract: Designs and techniques for manufacturing microelectronic antenna tuners are provided. An example microelectronic antenna system includes a radio frequency integrated circuit comprising a plurality of radio frequency signal ports disposed in a first area, a plurality of tuning devices disposed in a second area of the radio frequency integrated circuit, at least one antenna element disposed on a substrate coupled to the radio frequency integrated circuit, and at least one feedline disposed in the substrate and configured to communicatively couple the at least one antenna element, at least one of the plurality of tuning devices, and one of the plurality of radio frequency signal ports.
    Type: Grant
    Filed: September 25, 2021
    Date of Patent: April 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chuan Wang, Li Liu, Bhushan Shanti Asuri, Kevin Hsi-Huai Wang, Gurkanwal Singh Sahota
  • Publication number: 20240103356
    Abstract: An electronic device is provided. The electronic device includes a base and a conductive layer that is disposed on the base and patterned by a plurality of processes. The plurality of processes include providing a mask substrate. The mask substrate includes a first substrate and a patterned substrate. In the cross-sectional view, the width of the first substrate is greater than or equal to the width of the patterned substrate. The plurality of processes include arranging the mask substrate and the base correspondingly. The plurality of processes also include performing exposure and development processes on the conductive layer for patterning the conductive layer, and removing the mask substrate.
    Type: Application
    Filed: December 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsing LEE, Chin-Lung TING, Jung-Chuan WANG, Hong-Sheng HSIEH
  • Publication number: 20240105937
    Abstract: Provided is a production method of a high-rate lithium iron phosphate positive electrode material comprising first, weighing an iron source and a lithium source in a molar ratio of 1:1-1:1.05, then weighing 5-15% of carbon source and 0-1% of metal ion doping agent based on the total mass of the iron source and lithium source, adding water to the above weighed materials, ball milling and sand grinding the obtained slurry, so that the D50 after the sand grinding is controlled to be 100-200 nm, then spraying the mixture to obtain a precursor, putting the precursor into a sintering furnace for sintering at 650-700° C. under the protection of nitrogen gas, cooling to obtain a sintered material, then pulverizing the sintered material, sieving the pulverized material and removing iron to obtain the lithium iron phosphate. The prepared lithium iron phosphate has a good rate capability and a good cycle stability.
    Type: Application
    Filed: July 8, 2022
    Publication date: March 28, 2024
    Applicant: HUBEI WANRUN NEW ENERGY TECHNOLOGY CO., LTD.
    Inventors: Jiaojiao YANG, Qin WANG, Guozhang CHENG, Chuan GAO, Xu ZHAO, Suixi YU
  • Publication number: 20240103217
    Abstract: Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: Brian McGowan, Ping-Chuan Wang, Oscar Restrepo
  • Patent number: 11942971
    Abstract: Aspects described herein include devices and methods with chain routing of signals for massive antenna arrays. In some aspects, an apparatus is provided that includes a first millimeter wave (mmW) transceiver having a first port, a second port, one or more antenna elements, a plurality of chain mmW transceiver ports, and switching circuitry. The switching circuitry is controllable by control data to route portions of a merged clock and data signal and a merged control and data signal between a first route between the one or more antenna elements and the first port and a second route between the one or more antenna elements and the second port and a third route between the first port and the plurality of chain mmW transceiver ports and a fourth route between the second port and the plurality of chain mmW transceiver ports.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: March 26, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chuan Wang, Li Liu, Wu-Hsin Chen, Vinod Panikkath, Yunfei Feng, Muhammad Hassan
  • Patent number: 11941391
    Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Sarathy Jayakumar, Chuan Song, Ruixia Li, Xiaojin Yuan, Haiyue Wang, Chong Han
  • Patent number: 11942145
    Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20240094902
    Abstract: A method for selecting an application and associated operational guidance to utilize on a mobile device is disclosed. In one embodiment, such a method identifies a selected environment of interest. Within the selected environment, the method identifies one or more applications that are commonly utilized by users within the selected environment and documents the one or more applications. The method detects physical entry of a particular user into the selected environment and, in response to detecting the entry, automatically notifies the particular user of the one or more applications that are commonly utilized within the selected environment. In certain embodiments, the method enables the user to quickly launch the one or more applications and/or provides operational guidance to the user with regard to using the one or more applications. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Applicant: International Business Machines Corporation
    Inventors: Xiang Wei Li, Dong Chen, Ye Chuan Wang, Ting Ting Zhan, Ju Ling Liu, Yu An, Wei Yan