Patents by Inventor Chuan Wang
Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250087764Abstract: A configuration method for a plurality of serial codes of a battery management system, wherein the battery management system includes a master battery management device and a plurality of slave battery management devices. The configuration method comprises steps of: sending, by each slave battery management device, a notification message through a first communication interface, wherein each notification message includes an identification code of each slave battery management device; receiving, by the master battery management device, each notification message and acquiring each identification code from each notification message received; counting, by the master battery management device, a number of the identification codes and performing a configuration step when the number of the identification codes is determined to be equal to a predetermined number of connections. In the configuration step, the first to the last of the slave battery management devices are configured sequentially with a serial code.Type: ApplicationFiled: September 9, 2024Publication date: March 13, 2025Applicant: MOBILETRON ELECTRONICS CO., LTD.Inventors: PIN-HAO WANG, WEN-CHUAN HUNG
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Publication number: 20250088565Abstract: A service providing system includes a service-end device and a user-end device. The service-end device is used for providing at least one service identification information, and sending at least one activation signal within a preset range. The user-end device installs at least one service application program. When the user-end device appears in the preset range, it performs following procedures: receiving the at least one activation signal, and obtaining the service identification information provided by the service-end device according to the at least one activation signal; determining whether the service application program matches the service identification information or not; when determining that the service application program matches the service identification information, triggering the matched service application program; and establishing a two-way connection to the service-end device through the service application program.Type: ApplicationFiled: January 10, 2024Publication date: March 13, 2025Inventors: TSE-CHUAN WANG, HUNG-YUN HSIEH
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Publication number: 20250087635Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element stacking structure is disposed on a carrier structure to integrate multiple chips into a single package, so that the electronic package can meet with the requirements of miniaturization without increasing the layout area of the carrier structure.Type: ApplicationFiled: May 21, 2024Publication date: March 13, 2025Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Shu-Chuan CHI, Yih-Jenn JIANG, Cheng-Kai CHANG, Huan-Shiang LI, Yi-Chieh WANG
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Patent number: 12249636Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.Type: GrantFiled: December 10, 2021Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Hsuan Chen, Ping-Wei Wang
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Publication number: 20250073624Abstract: An in-mold piping filter includes: a join made by plastic injection molding and having a tubular body. Two ends of the tubular body are respectively formed with the opening, and the two openings provide a connection, so that a complete pipeline is constructed and fluid can be transported through the joint. Moreover, the filter member is integrally formed inside the tubular body during the injection molding, and the filter member includes a dividing plate. The dividing plate has a plurality of filter holes.Type: ApplicationFiled: September 5, 2023Publication date: March 6, 2025Inventor: CHIANG-CHUAN WANG
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Publication number: 20250081347Abstract: An electrical connection device includes a mother board and a daughter board. The mother board includes a first board body with at least one cavity and a first electrical contact printed on the first board body. The daughter board includes a second board body and a second electrical contact printed on the second board body. At least one of the daughter board and the mother board includes at least one contour feature integrally formed with at least one of the first board body and the second board body. When the second board body is inserted into the at least one cavity of the first board body, the second electrical contact is electrically connected to the first electrical contact, and the daughter board is positioned in the mother board through the at least one contour feature.Type: ApplicationFiled: August 30, 2024Publication date: March 6, 2025Applicant: Industrial Technology Research InstituteInventors: Chung-Wei Wang, Chen-Tsai Yang, Shu-Wei Kuo, Min-Hsiung Liang, Bor-Chuan Chuang
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Patent number: 12243918Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.Type: GrantFiled: June 10, 2022Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Hsiang Wu, Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12243912Abstract: Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.Type: GrantFiled: December 15, 2021Date of Patent: March 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chuan Yang, Wen-Chun Keng, Chong-De Lien, Shih-Hao Lin, Hsin-Wen Su, Ping-Wei Wang
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Publication number: 20250070064Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.Type: ApplicationFiled: January 3, 2024Publication date: February 27, 2025Inventors: Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Hsin-Feng Chen, Tsung-Chieh Hsiao, Chih Chuan Su, Dian-Hau Chen
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Publication number: 20250060839Abstract: A mouse structure includes a shell, a control circuit, a button and an elastic member. The shell includes a base and an upper cover. A boss extends from the upper cover towards the base. The control circuit includes a circuit board and a switch arranged thereon. The button comprises a hollow cylindrical body extending through the upper cover and having a pressing surface and a stop surface opposite each other. The elastic member comprises an embedded section snapped to the boss, a pressing part and an elastic part. The elastic part being connected between the embedded section and the pressing part and extending through into the hollow cylindrical body. The pressing part is elastically pressed against the stop surface to pull down the hollow cylindrical body, so that the pressing surface is attached to a surface of the switch.Type: ApplicationFiled: December 19, 2022Publication date: February 20, 2025Applicant: Voyetra Turtle Beach, Inc.Inventor: Wei Chuan WANG
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Publication number: 20250058353Abstract: A micro-electromechanical-system (MEMS) device may include a capacitive micromachined ultrasonic transducer (CMUT) that includes an actuation membrane and a sensing dielectric layer that are spaced apart by a cavity. The sensing dielectric layer may be formed such that the thickness of the sensing dielectric layer may extend the operational of the CMUT while enabling the CMUT to accommodate a sufficiently high direct current voltage bias for collapsed mode operation. In this way, the thickness of the sensing dielectric layer enables the CMUT to operate in the collapsed mode, which enables the CMUT to achieve greater sound pressure output relative to other operational modes and enables the frequency response of the CMUT to be adjustable, thereby enabling the frequency response to be optimized for specific use cases and applications.Type: ApplicationFiled: August 16, 2023Publication date: February 20, 2025Inventors: Chia-Ming HUNG, Wen-Chuan TAI, Chun-Heng CHEN, Shao-Da WANG, Hsiang-Fu CHEN
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Publication number: 20250058379Abstract: The present application provides a preparation method for iridium nanocrystal, including the following steps: mixing an iridium salt, an alcohol solvent and a centrifugal waste liquid to form a mixed solution, and adding an alkali solution in an inert atmosphere for a heating reaction. After centrifugation, an iridium nanocrystal is obtained. The centrifugal waste liquid is a waste liquid produced in the pre-synthesis process of iridium nanocrystal. The preparation method can shorten the reaction time, and the obtained iridium nanocrystal has the advantages of high yield and low cost.Type: ApplicationFiled: November 5, 2024Publication date: February 20, 2025Inventors: Yanfei WANG, Yinglong YU, Chenyi SHAO, Chuan LONG, Qinfeng ZHAO, Jingjing WANG, Yeheng HE, Qingxun LI
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Publication number: 20250063808Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.Type: ApplicationFiled: August 17, 2023Publication date: February 20, 2025Inventors: KUAN-TING PAN, JIA-CHUAN YOU, CHIA-HAO CHANG, KUO-CHENG CHIANG, CHIH-HAO WANG
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Publication number: 20250062088Abstract: An improved key structure for a keyboard may be installed on a keyboard iron plate and comprises lower housing and upper housings. The lower housing includes a lower peripheral wall which includes a lower bulge portion thereon, both side surfaces of the lower peripheral wall include a pair of elastic arms thereon that include a latching portion and a pulling portion thereon. The upper housing is assembled on the lower housing, and includes an upper bulge portion. The elastic arms extend from the bottom of the lower housing, the tops of the elastic arms are aligned with an upper surface of the lower bulge portion, and two sides of the elastic arms abut against the lower peripheral wall, so that the insertion force of the key structure is small, and the key structure is firmly buckled on the keyboard iron plate with a large buckling force.Type: ApplicationFiled: December 19, 2022Publication date: February 20, 2025Applicant: Voyetra Turtle Beach, Inc.Inventor: Wei Chuan WANG
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Publication number: 20250063792Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.Type: ApplicationFiled: December 1, 2023Publication date: February 20, 2025Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250058437Abstract: An impact tool includes a motor including or connected to a drive shaft for outputting power and is rotatable about a first axis, an impact assembly including a main shaft and a spring sleeved on the main shaft, a transmission assembly for transmitting the power output by the drive shaft to the main shaft, a main shaft bearing for supporting the main shaft, and a second bearing for supporting the drive shaft. The projections of the second bearing, the main shaft bearing and the spring on a reference plane perpendicular to the up and down direction have an overlapping region.Type: ApplicationFiled: November 1, 2024Publication date: February 20, 2025Inventors: Rui Xu, Yuyi Zheng, Chen Wang, Masatoshi Fukinuki, Biao Zhang, Hongtao Ke, Hengyong Hu, Chuan Geng, Xiaoyong Wang, Di Wu
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Patent number: 12226803Abstract: A device for separating and recovering flat-plate catalyst powder and a method for determining a wear ratio are provided. The device includes a powder separation unit and a powder recovery unit, a powder accumulation bin is respectively connected with a shell and a catalyst powder outlet, a cyclone outlet is configured on an inner side of a recovery shell, and a primary filter and a secondary filter are configured on an inner side wall of the recovery shell.Type: GrantFiled: June 29, 2023Date of Patent: February 18, 2025Assignees: HUANENG CHONGQING LUOHUANG POWER GENERATION CO., LTD, SUZHOU XIRE ENERGY SAVING ENVIRONMENTAL PROTECTION TECHNOLOGY CO., LTD.Inventors: Yingjie Bao, Jieyong Hao, Changkai Yu, Xun Wu, Xianchun Zhou, Yanxuan Liang, Rongfu Tang, Feiyun Chen, Bin Luo, Kaiyou Liao, Danping Zhang, Chao Li, Fanhai Kong, Lele Wang, Qiang Bao, Chuan He
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Publication number: 20250053279Abstract: The embodiments of the disclosure provide a method, apparatus, device and storage medium for presenting information, which relate to the technical field of computers. The method includes: obtaining object search information, in response to the object search information being object category information, determining a target object category corresponding to the object search information, and presenting object information of a plurality of target objects corresponding to the target object category in a search result presentation page; where all the plurality of target objects are different, and object information of a target object includes object attribute information and image resource information of the target object. By employing the above technical solution, when the user is searching the object category, object information of a plurality of target objects different from each other corresponding to the target object category is presented in the search result page.Type: ApplicationFiled: August 9, 2024Publication date: February 13, 2025Inventors: Jing LIN, Duanliang ZHOU, Long RU, Chao WU, Conghai YAO, Yelun LIU, Bin QIAN, Siyi YE, Jie WANG, Wenhao LI, Wenjing LIU, Shengan CAI, Tingting YANG, Yiwei WANG, Junjun YAO, Yifei QIU, Ju YANG, Yunfei SONG, Chuan ZHAO, Xianhui WEI, Xiaofeng WANG, Jianwen WU, Meng CHEN, Mang WANG, Peng HE, Kaijian LIU, Liangpeng XU, Yuhang LIU, Xiang XIAO, Runyu CHEN, Da LEI, Xiangnan LUO, Zheng PENG, Shaolong CHEN, Binghua XU, Hongtao XUE, Guorong ZHU, Qinglin XU, Pingping HUANG, Hongtao HU
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Publication number: 20250056867Abstract: An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.Type: ApplicationFiled: October 30, 2024Publication date: February 13, 2025Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250056862Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.Type: ApplicationFiled: October 30, 2024Publication date: February 13, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG