Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

Abstract: A key structure including a base plate, a thin film circuit, a display key, an elastic supporting member, and a lifting mechanism is provided. The thin film circuit is disposed on the base plate. The display key is disposed above the thin film circuit. The elastic supporting member is disposed between the display key and the thin film circuit. The lifting mechanism is disposed between the display key and the base plate.

Abstract: A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.

Abstract: A dual-standard AC smart charging pile includes a first charging gun, a first power supply circuit, a second charging gun, a second power supply circuit and a signal processing circuit. Each of the two charging guns comprises a charging port conforming to different specifications. Each of the two power supply circuits is electrically connected to the corresponding charging gun, and is respectively configured to provide power to the corresponding charging gun based on different specifications. The signal processing circuit is electrically connected to the first charging gun, the second charging gun, the first power supply circuit and the second power supply circuit, and is configured to control one or both of the first power supply circuit and the second power supply circuit according to one or both of a first trigger time point of the first charging gun and a second trigger time point of the second charging gun.

Abstract: An AC smart charging pile includes a charging gun, a power supply circuit, a communication transmission unit and a signal processing circuit. The power supply circuit is connected to the charging gun, and configured to provide power to the charging gun. The communication transmission unit is configured to obtain charging data from a user device or a management center. The signal processing circuit is connected to the power supply circuit and the communication transmission unit, and configured to control charging power of the power supply circuit.

Abstract: An electric vehicle smart charging system includes at least one smart charging pile and a cloud management center. Each of the at least one smart charging pile includes a charging gun, a power supply circuit, a camera module and a signal processing circuit. The power supply circuit is configured to provide electric power to the charging gun. The camera module is configured to capture at least one image associated with a vehicle. The signal processing circuit has at least one recognition model and is configured to use the at least one recognition model to perform an edge computation on the at least one image and control the power supply circuit according to a result of the edge computation. The cloud management center is configured to update the at least one recognition model of the signal processing circuit according to the result from the signal processing circuit.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: The present invention discloses a barbeque grill lift cover structure comprising a combining base disposed separately at corresponding positions on both sides of the body, and a pair of link rods installed with an interval apart and at rear laterals of the combining base, and another end of the link rod is pivotally coupled to both sides of the cover separately to constitute the barbeque grill lift cover structure of the invention, and the link rods at both sides of the body and the cover can be pivotally coupled, such that when the cover is lifted open, the link rods are pivotally turned and guided to achieve a smooth lifting movement and maintain the lift cover stably.

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Abstract: A photoelectric conversion is capable of converting the light energy into electrical power, comprising a tempered glass layer, a lens module, a substrate and a heat sink unit, wherein the lens module is formed from a plurality of lens units, which locate at one side of the tempered glass layer. A gap is formed via a plurality of protruding poles located between the lens units and the tempered glass layer. The gap is filled with transparent rubbers. A plurality of receiving units is located one side of the substrate for dissipating heat energy from the receiving units. The light energy is converted through the receiving units into the electrical energy by focusing the light to the receiving units via the tempered glass layer and the lens module.

Abstract: A light collector is capable of collecting a incident light, comprises a light condenser having an incident surface and an exit surface, a light reflecting unit having two end surfaces and a receiving unit, wherein the incident light enters through the incident surface of the light condenser and the light condenser alters an optical distance and an optical direction of the incident light so that the incident light is transmitted evenly to the exit surface of the light condenser. A reflecting layer is positioned inside the light reflecting unit, and the light condenser is positioned at one end surface of the light reflecting unit in order to receive the incident light from the exit surface. The receiving unit is used to receive the incident light exiting from the light reflecting unit so that a photoelectrical process is carried out and the incident light is converted into electrical energy.

Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.