Patents by Inventor Chuan-Yi Lin

Chuan-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12236627
    Abstract: A system and method for measuring circumference of human body are provided. The system includes a 3D sensor configured to obtain a 3D information of a human body with a garment on; a temperature sensor configured to obtain a thermal information of the human body with the garment on; a calibration unit configured to obtain a calibration parameter of the 3D sensor and the temperature sensor; a model generation unit configured to integrate the 3D information and the thermal information according to the calibration parameter to generate a 3D temperature model of the human body with the garment on; and a circumference computation unit configured to retrieve an original profile information corresponding to a target location from the 3D temperature model, and correct the original profile information according to a thermal compensation mechanism to obtain a real circumference of the human body corresponding to the target location.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: February 25, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shang-Yi Lin, Tung-Fa Liou, Chuan-Chi Wang
  • Publication number: 20240217379
    Abstract: A dual-standard AC smart charging pile includes a first charging gun, a first power supply circuit, a second charging gun, a second power supply circuit and a signal processing circuit. Each of the two charging guns comprises a charging port conforming to different specifications. Each of the two power supply circuits is electrically connected to the corresponding charging gun, and is respectively configured to provide power to the corresponding charging gun based on different specifications. The signal processing circuit is electrically connected to the first charging gun, the second charging gun, the first power supply circuit and the second power supply circuit, and is configured to control one or both of the first power supply circuit and the second power supply circuit according to one or both of a first trigger time point of the first charging gun and a second trigger time point of the second charging gun.
    Type: Application
    Filed: July 18, 2023
    Publication date: July 4, 2024
    Applicants: MICRO-STAR INT’L CO.,LTD., MSI COMPUTER (SHENZHEN) CO.,LTD.
    Inventors: Chuan Yi LIN, Hong Hen LIN, Chi Yang LIN, Chien-Chi HSU
  • Publication number: 20240217377
    Abstract: An AC smart charging pile includes a charging gun, a power supply circuit, a communication transmission unit and a signal processing circuit. The power supply circuit is connected to the charging gun, and configured to provide power to the charging gun. The communication transmission unit is configured to obtain charging data from a user device or a management center. The signal processing circuit is connected to the power supply circuit and the communication transmission unit, and configured to control charging power of the power supply circuit.
    Type: Application
    Filed: October 17, 2023
    Publication date: July 4, 2024
    Applicants: MICRO-STAR INT’L CO.,LTD., MSI COMPUTER (SHENZHEN) CO.,LTD.
    Inventors: Chuan Yi LIN, Hong Hen LIN, Chi Yang LIN
  • Publication number: 20240217375
    Abstract: An electric vehicle smart charging system includes at least one smart charging pile and a cloud management center. Each of the at least one smart charging pile includes a charging gun, a power supply circuit, a camera module and a signal processing circuit. The power supply circuit is configured to provide electric power to the charging gun. The camera module is configured to capture at least one image associated with a vehicle. The signal processing circuit has at least one recognition model and is configured to use the at least one recognition model to perform an edge computation on the at least one image and control the power supply circuit according to a result of the edge computation. The cloud management center is configured to update the at least one recognition model of the signal processing circuit according to the result from the signal processing circuit.
    Type: Application
    Filed: December 11, 2023
    Publication date: July 4, 2024
    Applicant: MICRO-STAR INT’L CO.,LTD.
    Inventors: Chuan Yi LIN, Chung Ming CHAN, Ming Huei CHANG, Szu Hsien WU
  • Patent number: 8779572
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8742583
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20140054761
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Application
    Filed: November 5, 2013
    Publication date: February 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8609506
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8314483
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20120266857
    Abstract: The present invention discloses a barbeque grill lift cover structure comprising a combining base disposed separately at corresponding positions on both sides of the body, and a pair of link rods installed with an interval apart and at rear laterals of the combining base, and another end of the link rod is pivotally coupled to both sides of the cover separately to constitute the barbeque grill lift cover structure of the invention, and the link rods at both sides of the body and the cover can be pivotally coupled, such that when the cover is lifted open, the link rods are pivotally turned and guided to achieve a smooth lifting movement and maintain the lift cover stably.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 25, 2012
    Inventor: Chuan-Yi LIN
  • Publication number: 20120112322
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Application
    Filed: January 16, 2012
    Publication date: May 10, 2012
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Patent number: 8168529
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: May 1, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20110253883
    Abstract: A light collector is capable of collecting a incident light, comprises a light condenser having an incident surface and an exit surface, a light reflecting unit having two end surfaces and a receiving unit, wherein the incident light enters through the incident surface of the light condenser and the light condenser alters an optical distance and an optical direction of the incident light so that the incident light is transmitted evenly to the exit surface of the light condenser. A reflecting layer is positioned inside the light reflecting unit, and the light condenser is positioned at one end surface of the light reflecting unit in order to receive the incident light from the exit surface. The receiving unit is used to receive the incident light exiting from the light reflecting unit so that a photoelectrical process is carried out and the incident light is converted into electrical energy.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 20, 2011
    Inventors: Chien-Feng LIN, Cheng-Yu Huang, Te-Kai Ku, Chuan-Yi Lin
  • Publication number: 20110253194
    Abstract: A photoelectric conversion is capable of converting the light energy into electrical power, comprising a tempered glass layer, a lens module, a substrate and a heat sink unit, wherein the lens module is formed from a plurality of lens units, which locate at one side of the tempered glass layer. A gap is formed via a plurality of protruding poles located between the lens units and the tempered glass layer. The gap is filled with transparent rubbers. A plurality of receiving units is located one side of the substrate for dissipating heat energy from the receiving units. The light energy is converted through the receiving units into the electrical energy by focusing the light to the receiving units via the tempered glass layer and the lens module.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 20, 2011
    Inventors: Chien-Feng LIN, Cheng-Yu Huang, Te-Kai Ku, Chuan-Yi Lin
  • Patent number: 7825024
    Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: November 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Song-Bor Lee, Ching-Kun Huang, Sheng-Yuan Lin
  • Publication number: 20100187670
    Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
    Type: Application
    Filed: November 12, 2009
    Publication date: July 29, 2010
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20100187671
    Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
    Type: Application
    Filed: November 13, 2009
    Publication date: July 29, 2010
    Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
  • Publication number: 20100130003
    Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 27, 2010
    Inventors: Chuan-Yi Lin, Song-Bor Lee, Ching-Kun Huang, Sheng-Yuan Lin
  • Patent number: 7645973
    Abstract: A solar-tracking power generating apparatus includes a plurality of sensing units having a directional light-extraction member each, a plurality of solar batteries associated with a light-gathering device each, and a solar trajectory simulation unit. Therefore, the solar-tracking power generating apparatus enables more accurate tracking of solar position and focusing of more sunlight on the solar batteries, so that the solar batteries could absorb more sunlight and convert the same into an increased amount of electric power.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 12, 2010
    Inventors: Chien-Feng Lin, Chuan-Yi Lin, Cheng-Min Chen
  • Patent number: D656774
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: April 3, 2012
    Assignee: Voka Enterprise Co., Ltd.
    Inventor: Chuan-Yi Lin