Patents by Inventor Chuan-Yi Lin

Chuan-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100130003
    Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 27, 2010
    Inventors: Chuan-Yi Lin, Song-Bor Lee, Ching-Kun Huang, Sheng-Yuan Lin
  • Patent number: 7645973
    Abstract: A solar-tracking power generating apparatus includes a plurality of sensing units having a directional light-extraction member each, a plurality of solar batteries associated with a light-gathering device each, and a solar trajectory simulation unit. Therefore, the solar-tracking power generating apparatus enables more accurate tracking of solar position and focusing of more sunlight on the solar batteries, so that the solar batteries could absorb more sunlight and convert the same into an increased amount of electric power.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: January 12, 2010
    Inventors: Chien-Feng Lin, Chuan-Yi Lin, Cheng-Min Chen
  • Publication number: 20090095342
    Abstract: A solar-tracking power generating apparatus includes a plurality of sensing units having a directional light-extraction member each, a plurality of solar batteries associated with a light-gathering device each, and a solar trajectory simulation unit. Therefore, the solar-tracking power generating apparatus enables more accurate tracking of solar position and focusing of more sunlight on the solar batteries, so that the solar batteries could absorb more sunlight and convert the same into an increased amount of electric power.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 16, 2009
    Inventors: Chien-Feng Lin, Chuan-Yi Lin, Cheng-Min Chen
  • Patent number: 7459756
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: December 2, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
  • Patent number: 7271431
    Abstract: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: September 18, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Shien-Yang Wu, Yee-Chia Yeo
  • Publication number: 20060286740
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 21, 2006
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh LIN, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
  • Patent number: 7112483
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: September 26, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
  • Patent number: 7078723
    Abstract: A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: July 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Wen-Chin Lee, Sun-Jay Chang, Shien-Yang Wu
  • Publication number: 20050287779
    Abstract: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 29, 2005
    Inventors: Chuan-Yi Lin, Shien-Yang Wu, Yee-Chia Yeo
  • Publication number: 20050224897
    Abstract: A high-K gate dielectric stack for a MOSFET gate structure to reduce Voltage threshold (Vth) shifts and method for forming the same, the method including providing a high-K gate dielectric layer over a semiconductor substrate; forming a buffer dielectric layer on the high-K gate dielectric including a dopant selected from the group consisting of a metal, a semiconductor, and nitrogen; forming a gate electrode layer on the buffer dielectric layer; and, lithographically patterning the gate electrode layer and etching to form a gate structure.
    Type: Application
    Filed: March 26, 2004
    Publication date: October 13, 2005
    Inventors: Shang-Chih Chen, Chih-Hao Wang, Yee-Chia Yeo, Feng-Der Chin, Chuan-Yi Lin
  • Patent number: 6905922
    Abstract: A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: June 14, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yi Lin, Yee-Chia Yeo
  • Publication number: 20050074932
    Abstract: A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 7, 2005
    Inventors: Chuan-Yi Lin, Yee-Chia Yeo
  • Publication number: 20050045965
    Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
    Type: Application
    Filed: April 23, 2004
    Publication date: March 3, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu