Abstract: A multiplexer applied to a display device includes: a plurality of switching units, electrically coupled to a data driver and a plurality of pixel units, where the switching units are adapted to receive a plurality of input display data signals output by the data driver, and the switching units output a plurality of output display data signals to the electrically coupled pixel units, where each of the switching units includes a plurality of switch units, configuration locations of the switch units in each of the switching units are the same as, and some of the switch units configured at a same configuration location in the different switching units are electrically coupled to different control signal lines and have different wiring lengths, where the wiring lengths are distances between the switch units and the control signal lines.

Abstract: A shift register and a touch display apparatus thereof are provided. The shift register includes a voltage setting unit, a driving unit, a control unit, a discharge unit, a first compensation transistor, and a second compensation transistor. The voltage setting unit sets a terminal voltage of an internal terminal. The driving unit is coupled to the internal terminal to provide a gate signal and a driving signal. The control unit receives the terminal voltage to provide a control signal. The discharge unit discharges the terminal voltage and the gate signal according to the control signal. The first compensation transistor and the second compensation transistor are coupled in series between a touch enable signal and the internal terminal, and control terminals of the first compensation transistor and the second compensation transistor receive the terminal voltage and the touch enable signal, respectively.

Abstract: Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n?1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.

Abstract: An anti-interference display panel includes a source driving chip, a switching signal line, a multiplexer, and an anti-interference signal line. The source driving chip is configured to generate a data signal. The switching signal line is configured to transmit a switching signal. The multiplexer is configured to receive the data signal and the switching signal, and is configured to output the data signal according to the switching signal. The anti-interference signal line is configured to transmit an anti-interference signal. An equivalent resistor and an equivalent capacitor are formed on the anti-interference signal line, and resistance of the equivalent resistor is approximate to resistance of a load resistor coupled to the switching signal line, and capacitance of the equivalent capacitor is approximate to capacitance of a load capacitor coupled to the switching signal line.

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

Abstract: A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.

Abstract: A shift register including a voltage set unit, a driver unit, a control unit, a first transistor, a second transistor, a third transistor and a fourth transistor is provided. The voltage set unit provides a terminal voltage. The driver unit provides a main gate signal according to the terminal voltage and a clock signal. The control unit provides a control signal. The first transistor receives the terminal voltage, a level reference voltage and the control signal. The second transistor is coupled to the first transistor and receives a low voltage and the control signal. The third transistor receives the terminal voltage, a level reference voltage and a gate reference signal. The fourth transistor is coupled to the third transistor and receives the low voltage and the gate reference signal.

Abstract: A touch display apparatus includes a touch driver and a display driver. The touch driver outputs touch signals to drive a touch panel. The display driver outputs scan signals to drive a display panel. A display driver has a plurality of shift registers, and each of the plurality of shift registers includes a pull-up unit, a driving unit, a pull-down unit and a holding unit. The pull-up unit is electrically connected to a driving node for outputting a driving voltage. The driving unit is electrically connected to the driving node for outputting a first scan signal according to a clock. A pull-down unit is electrically connected to the driving node and the output terminal, for pulling down the voltage level of the driving voltage and the first scan signal, respectively. The holding unit is electrically connected to the driving node.

Abstract: A touch display apparatus includes a touch driver and a display driver. The touch driver outputs touch signals to drive a touch panel. The display driver outputs scan signals to drive a display panel. A display driver has a plurality of shift registers, and each of the plurality of shift registers includes a pull-up unit, a driving unit, a pull-down unit and a holding unit. The pull-up unit is electrically connected to a driving node for outputting a driving voltage. The driving unit is electrically connected to the driving node for outputting a first scan signal according to a clock. A pull-down unit is electrically connected to the driving node and the output terminal, for pulling down the voltage level of the driving voltage and the first scan signal, respectively. The holding unit is electrically connected to the driving node.

Abstract: A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first end of each buffer handling unit is used to independently transfer data to or from the associated master device. A second end of each buffer handling unit is coupled to a buffer switch. A time slot controller defines a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes a first ECC codec that selectively performs different error corrections with different parameters; means for providing a selected parameter to the ECC codec for initializing the ECC codec; and a second ECC codec that corrects the selected error-prone parameter in order to provide an error-free parameter to the first ECC codec.

Abstract: A time-sharing buffer access system manages a buffer among plural master devices. Plural buffer handling units are operable to associatively couple the master devices, respectively, and a first end of each buffer handling unit is used to independently transfer data to or from the associated master device. A second end of each buffer handling unit is coupled to a buffer switch. A time slot controller defines a time slot, during which one of the buffer handling units is selected by the buffer switch such that data are only transferred between the selected buffer handling unit and the buffer.

Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter.

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus.

Abstract: A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced.

Abstract: A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter.

Abstract: A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters.

Abstract: An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding.