Patents by Inventor Chuck Jang
Chuck Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7910429Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.Type: GrantFiled: April 7, 2004Date of Patent: March 22, 2011Assignee: ProMOS Technologies, Inc.Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chunchieh Huang, Jin-Ho Kim, Vei-Han Chan, Chung Wai Leung, Chia-Shun Hsiao, George Kovall, Steven Ming Yang
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Patent number: 7323729Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.Type: GrantFiled: May 4, 2006Date of Patent: January 29, 2008Assignee: Promos Technologies Inc.Inventors: Zhong Dong, Chuck Jang, Chia-Shun Hsiao
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Patent number: 7297597Abstract: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height.Type: GrantFiled: July 23, 2004Date of Patent: November 20, 2007Assignee: Promos Technologies, Inc.Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chia-Shun Hsiao
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Publication number: 20070264776Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.Type: ApplicationFiled: May 8, 2007Publication date: November 15, 2007Inventors: Zhong Dong, Chuck Jang, Chunchieh Huang
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Patent number: 7229880Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.Type: GrantFiled: November 19, 2003Date of Patent: June 12, 2007Assignee: ProMOS Technologies Inc.Inventors: Zhong Dong, Chuck Jang, Chunchieh Huang
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Patent number: 7122415Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.Type: GrantFiled: September 12, 2002Date of Patent: October 17, 2006Assignee: ProMOS Technologies, Inc.Inventors: Chuck Jang, Zhong Dong, Vei-Han Chan, Ching-Hwa Chen
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Publication number: 20060211270Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950 ° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.Type: ApplicationFiled: May 4, 2006Publication date: September 21, 2006Inventors: Zhong Dong, Chuck Jang, Chia-Shun Hsiao
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Patent number: 7087998Abstract: A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.Type: GrantFiled: August 17, 2004Date of Patent: August 8, 2006Assignee: ProMOS Technology, Inc.Inventors: Tai-Peng Lee, Ching-Yueh Hu, Chuck Jang
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Patent number: 7071127Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.Type: GrantFiled: May 20, 2003Date of Patent: July 4, 2006Assignee: ProMOS Technologies, Inc.Inventors: Zhong Dong, Chuck Jang, Chia-Shun Hsiao
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Patent number: 7026172Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.Type: GrantFiled: October 22, 2001Date of Patent: April 11, 2006Assignee: ProMOS Technologies, Inc.Inventors: Tai-Peng Lee, Chuck Jang
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Patent number: 7001810Abstract: The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.Type: GrantFiled: January 30, 2004Date of Patent: February 21, 2006Assignee: ProMOS Technologies Inc.Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen
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Publication number: 20060017092Abstract: Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height.Type: ApplicationFiled: July 23, 2004Publication date: January 26, 2006Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chia-Shun Hsiao
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Publication number: 20060008997Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.Type: ApplicationFiled: August 4, 2005Publication date: January 12, 2006Inventors: Chuck Jang, Zhong Dong, Vei-Han Chan, Ching-Hwa Chen
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Publication number: 20050227437Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.Type: ApplicationFiled: April 7, 2004Publication date: October 13, 2005Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chunchieh Huang, Jin-Ho Kim, Vei-Han Chan, Chung Leung, Chia-Shun Hsiao, George Kovall, Steven Yang
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Patent number: 6924542Abstract: A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.Type: GrantFiled: July 29, 2004Date of Patent: August 2, 2005Assignee: ProMos Technologies, Inc.Inventors: Hua Ji, Dong Jun Kim, Jin-Ho Kim, Chuck Jang
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Publication number: 20050106793Abstract: An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell.Type: ApplicationFiled: November 19, 2003Publication date: May 19, 2005Inventors: Zhong Dong, Chuck Jang, Chunchieh Huang
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Patent number: 6893920Abstract: A thin buffer layer of SiON is formed on the top surface of the floating gate, in order to protect the polysilicon surface from attack by atomic chlorine produced during the formation of the high temperature oxide of the ONO stack. The buffer layer can also be formed on other dielectric surfaces which are otherwise subject to adverse conditions in subsequent processing, such as the nitride layer in the ONO dielectric stack.Type: GrantFiled: September 12, 2002Date of Patent: May 17, 2005Assignee: ProMOS Technologies, Inc.Inventors: Zhong Dong, Chuck Jang
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Patent number: 6881668Abstract: A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.Type: GrantFiled: September 5, 2003Date of Patent: April 19, 2005Assignee: Mosel Vitel, Inc.Inventors: Tai-Peng Lee, Ching-Yueh Hu, Chuck Jang
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Publication number: 20050051865Abstract: A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.Type: ApplicationFiled: August 17, 2004Publication date: March 10, 2005Inventors: Tai-Peng Lee, Ching-Yueh Hu, Chuck Jang
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Publication number: 20050051864Abstract: A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.Type: ApplicationFiled: September 5, 2003Publication date: March 10, 2005Inventors: Tai-Peng Lee, Ching-Yueh Hu, Chuck Jang