Patents by Inventor Chueh Yang
Chueh Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170309485Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.Type: ApplicationFiled: April 25, 2016Publication date: October 26, 2017Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
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Patent number: 9793105Abstract: The invention provides a fabricating method of a FinFET, comprising: providing a substrate having fin structures; depositing an dielectric layer on the substrate filling between the fin structures; forming recesses to reveal a portion of the fin structure by removing a portion of the dielectric layer; performing a cleaning process on using a cleaning solution selected from one of a first solution, consisting of dHF and H2O2, and a second solution, consisting of dHF and DIO3; forming a gate structure across on the fin structures; and forming a source/drain structure on the substrate at two lateral sides of the gate structure. The present invention also provides a fabricating method of a FinFET having an improved cleaning step using a cleaning solution having one of a third solution, consisting of dHF and DIO3, and a fourth solution, consisting of NH4OH and DIO3 before formation of the source/drain structure.Type: GrantFiled: August 2, 2016Date of Patent: October 17, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen, Yi-Liang Ye
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Publication number: 20170263730Abstract: A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Inventors: Chun-Wei Yu, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9748111Abstract: A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.Type: GrantFiled: February 1, 2016Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20170243749Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.Type: ApplicationFiled: February 22, 2016Publication date: August 24, 2017Inventors: Chueh-Yang Liu, Chun-Wei Yu, Yu-Ying Lin, Yu-Ren Wang
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Patent number: 9741572Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.Type: GrantFiled: February 22, 2016Date of Patent: August 22, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chueh-Yang Liu, Chun-Wei Yu, Yu-Ying Lin, Yu-Ren Wang
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Patent number: 9741818Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.Type: GrantFiled: December 9, 2015Date of Patent: August 22, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chueh-Yang Liu, Yu-Ying Lin, I-cheng Hu, Tien-I Wu, Yu-Shu Lin, Yu-Ren Wang
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Semiconductor device having the insulating layers cover a bottom portion of the fin shaped structure
Patent number: 9728397Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.Type: GrantFiled: May 10, 2016Date of Patent: August 8, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsu Ting, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang -
Publication number: 20170221723Abstract: A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.Type: ApplicationFiled: February 1, 2016Publication date: August 3, 2017Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9716165Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 21, 2016Date of Patent: July 25, 2017Assignee: United Microelectronics CorporationInventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Publication number: 20170200824Abstract: A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.Type: ApplicationFiled: March 26, 2017Publication date: July 13, 2017Inventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen
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Publication number: 20170179286Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20170170296Abstract: A manufacturing method of a semiconductor structure for improving quality of an epitaxial layer is provided in the present invention. The manufacturing method includes the following steps. A gate structure is formed on a semiconductor substrate, and two lightly doped regions are formed in the semiconductor substrate at two sides of the gate structure. A capping layer is formed on the gate structure and the lightly doped regions. Two epitaxial layers are formed at the two sides of the gate structure after the step of forming the capping layer. An oxide film formed on the lightly doped regions will influence the growth condition of the epitaxial layers. A removing process is performed to remove the oxide film on the lightly doped regions before the step of forming the capping layer so as to improve the quality of the epitaxial layers.Type: ApplicationFiled: December 9, 2015Publication date: June 15, 2017Inventors: Chueh-Yang Liu, Yu-Ying Lin, I-cheng Hu, Tien-I Wu, Yu-Shu Lin, Yu-Ren Wang
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Publication number: 20170162389Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Kuang-Hsiu Chen, Yi-Liang Ye, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9646889Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.Type: GrantFiled: January 21, 2016Date of Patent: May 9, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen
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Patent number: 9633904Abstract: A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.Type: GrantFiled: November 15, 2016Date of Patent: April 25, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9627534Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, an ILD layer on the semiconductor substrate, a gate in the ILD layer, an offset liner on a sidewall of the gate, a spacer on the offset liner, a dense oxide film on the spacer, a contact etch stop layer on the dense oxide film, and a contact plug adjacent to the contact etch stop layer. The semiconductor device further includes a source region in the semiconductor substrate and a drain region spaced apart from the source region. A channel is located between the source region and the drain region.Type: GrantFiled: November 20, 2015Date of Patent: April 18, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Yi-Liang Ye, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9613808Abstract: A method of forming a multilayer hard mask includes the following steps. An unpatterned multilayer hard mask is formed on a semiconductor substrate. The unpatterned multilayer hard mask includes a first hard mask layer formed on the semiconductor substrate and a second hard mask layer directly formed on the first hard mask layer. A treatment is performed on a top surface of the first hard mask layer before the step of forming the second hard mask layer, and the treatment is configured to remove impurities on the first hard mask layer and form dangling bonds on the top surface of the first hard mask layer. Defects related to the first hard mask layer and the second hard mask layer may be reduced, and the manufacturing yield may be enhanced accordingly.Type: GrantFiled: January 19, 2016Date of Patent: April 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9570315Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).Type: GrantFiled: March 18, 2015Date of Patent: February 14, 2017Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Chueh-Yang Liu, Yi-Liang Ye, Ted Ming-Lang Guo, Yu-Ren Wang
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Patent number: 9530886Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, and a plurality of hyper-sigma (?) shaped epitaxial stressors. The substrate includes a first semiconductor material, and the hyper-? shaped epitaxial stressors include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The hyper-? shaped epitaxial stressors respectively include a first portion, a second portion and a neck physically connecting the first portion and the second portion. The first portion includes a pair of first tips pointing toward the gate structure in a cross-sectional view. The second portion includes a pair of second tips pointing toward the gate structure in the cross-sectional view. The neck includes a first slanted surface in the first portion and a second slanted surface in the second portion.Type: GrantFiled: December 21, 2015Date of Patent: December 27, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Neng-Hui Yang