Abstract: A method of forming patterns includes forming a photoresist film on a substrate. The photoresist film is exposed with a first dose of light to form a first area and a second area in the photoresist film. A first hole and a second hole are formed by removing the first area and the second area with a first developer. The photoresist film is re-exposed with a second dose of the light to form a third area in the photoresist film between the first hole and the second hole. A third hole is formed between the first hole and the second hole by removing the third area with a second developer.

Abstract: In a method of forming a pattern, a photoresist pattern is formed on a substrate including an etching target layer. A surface treatment is performed on the photoresist pattern to form a guide pattern having a higher heat-resistance than the photoresist pattern. A material layer including a block copolymer including at least two polymer blocks is coated on a portion of the substrate exposed by the guide pattern. A micro-phase separation is performed on the material layer to form a minute pattern layer including different polymer blocks arranged alternately. At least one polymer block is removed from the minute pattern layer to form a minute pattern mask. The etching target layer is etched by using the minute pattern mask to form a pattern. Minute patterns may be formed utilizing a less complex process that those employed during conventional processes of forming a minute pattern.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.

Abstract: A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be positioned below the plasma generating unit. A reflector may be arranged below the grid system and may include parallel reflecting plates for converting the ions accelerated from the grid system into neutral beams.

Abstract: An apparatus and/or method for controlling an ion beam may be provided, and/or a method for preparing an extraction electrode for the same may be provided. In the apparatus, a plurality of extraction electrodes may be disposed in a path of an ion beam. At least one extraction electrode may include a plurality of sub-grids.

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat into a furnace and thermally treating the boat under an oxygen atmosphere.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat into a furnace and thermally treating the boat under an oxygen atmosphere.

Abstract: Example embodiments of the present invention provide a reflector for generating a neutral beam and a substrate processing apparatus including the same. The reflector may include at least one reflecting plate including a reflecting layer onto which an ion beam collides and a supporting layer. The reflecting layer may reflect and convert the ion beam into a neutral beam, and the supporting layer may reduce thermal deformation of the reflecting layer.

Abstract: An ion beam apparatus includes a plasma chamber with a grid assembly installed at one end of the plasma chamber and a plasma sheath controller disposed between the plasma chamber and the grid assembly. The grid assembly includes first ion extraction apertures. The plasma sheath controller includes second ion extraction apertures smaller than the first ion extraction apertures. When the plasma sheath controller is used in this configuration, the surface of the plasma takes on a more planar configuration adjacent the controller so that ions, extracted from the plasma in a perpendicular direction to the plasma surface, pass cleanly through the apertures of the grid assembly rather than collide with the sidewalls of the grid assembly apertures. A semiconductor manufacturing apparatus and method for forming an ion beam are also provided.

Abstract: Provided is a semiconductor apparatus using an ion beam. The semiconductor apparatus may include a first grid to which a voltage applied. The voltage applied to the first grid may have the same potential level as that of a reference voltage applied to a wall portion of a plasma chamber in which plasma may be generated. The first grid may adjoin the plasma. Therefore, a potential level difference between the first grid and the wall portion of the plasma chamber may be zero, and thus the plasma may be stable.

Abstract: An apparatus and/or method for controlling an ion beam may be provided, and/or a method for preparing an extraction electrode for the same may be provided. In the apparatus, a plurality of extraction electrodes may be disposed in a path of an ion beam. At least one extraction electrode may include a plurality of sub-grids.

Abstract: A method of forming a photoresist pattern comprises providing a semiconductor substrate on which a layer to be etched is formed.

Abstract: Example embodiments of the present invention provide a reflector for generating a neutral beam and a substrate processing apparatus including the same. The reflector may include at least one reflecting plate including a reflecting layer onto which an ion beam collides and a supporting layer. The reflecting layer may reflect and convert the ion beam into a neutral beam, and the supporting layer may reduce thermal deformation of the reflecting layer.

Abstract: A substrate processing apparatus may include a processing chamber including a plasma generating unit arranged in an upper region thereof. A grid system, which may extract ions from plasma formed by the plasma generating unit and may accelerate the ions to have substantially uniform directivity. The grid system may be positioned below the plasma generating unit. A reflector may be arranged below the grid system and may include parallel reflecting plates for converting the ions accelerated from the grid system into neutral beams.