Abstract: A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function block associated with the selected interface. When the selected interface is the only active interface, all function blocks in the memory card may be reset. If interfaces other than the selected interface are active, only the selected interface may be reset.

Abstract: A method of operating a multi-interface memory card including a first interface supporting a universal serial bus (USB) data transfer protocol and the second interface supporting an inter-chip USB (IC-USB) data transfer protocol includes; selecting either the first interface or the second interface to facilitate data communication between the multi-interface memory card and a host connected to the multi-interface memory card via a USB connection by comparing a level of a power-on voltage received from the host with a reference voltage level, and thereafter determining whether a reset signal has been received from the host.

Abstract: A semiconductor device includes at least one endpoint communicating with a host, and an endpoint controller dividing each of the at least one endpoint into a majority of sub-endpoints and performing numbering to each of the divided sub-endpoints. The endpoint controller transmits a packet generated by the host to any one of the sub-endpoints.

Abstract: Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: A method of operating a multi-interface memory card including a first interface supporting a universal serial bus (USB) data transfer protocol and the second interface supporting an inter-chip USB (IC-USB) data transfer protocol includes; selecting either the first interface or the second interface to facilitate data communication between the multi-interface memory card and a host connected to the multi-interface memory card via a USB connection by comparing a level of a power-on voltage received from the host with a reference voltage level, and thereafter determining whether a reset signal has been received from the host.

Abstract: A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: Provided are a Radio Frequency IDentification (RFID) tag with a signal reception method. The RFID tag includes a demodulator that receives a read signal containing read data. The demodulator includes; a voltage generating circuit that provides a first voltage signal and a second voltage signal derived from the received read signal, an inverter that provides a data pulse signal indicative of the read data by inverting the second voltage signal using an inverting voltage defined in relation to the first voltage signal, and a buffer that recovers the read data by buffering the data pulse signal.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A semiconductor device includes at least one endpoint communicating with a host, and an endpoint controller dividing each of the at least one endpoint into a majority of sub-endpoints and performing numbering to each of the divided sub-endpoints. The endpoint controller transmits a packet generated by the host to any one of the sub-endpoints.

Abstract: An electronic device includes a universal serial bus (USB) interface therein. This USB interface is configured to support at least first and second different USB interface standards. These different interface standards are selected by the electronic device in response to comparing a voltage level of a signal provided to said USB interface relative to a reference voltage generated within the electronic device. The signal provided to the USB may be a power supply signal, the first USB standard may be a USB 2.0 interface standard and the second USB standard may be an inter-chip USB interface standard.

Abstract: A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: An encryption processor, for storing encrypted data in a memory chip of a memory card, includes a FIFO memory for sequentially outputting m-bit data in response to a first signal, and an encryption key generator for generating m-bit encrypted keys (m being a positive integer) in response to a second signal and for sequentially outputting the keys in response to a third signal. A logic operator performs a logic operation on the data from the FIFO memory with the keys from the encryption key generator during a data write operation to sequentially encrypt the data. The logic operator performs a logic operation on the encrypted data received from a memory interface with the keys output from the encryption key generator during a data read operation in order to sequentially decode the encrypted data. The second signal is simultaneously generated with one of the write command or the read command.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: A method and apparatus for resetting a memory card having a plurality of interfaces and a plurality of function blocks, wherein each function block may be associated with a corresponding interface, may include detecting a reset signal for a selected interface of the plurality of interfaces, and interrupting a function block associated with the selected interface. When the selected interface is the only active interface, all function blocks in the memory card may be reset. If interfaces other than the selected interface are active, only the selected interface may be reset.